FEDL620Q130B-01

ML620Q131B/2B/3B/4B/5B/6B

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• Reset

‒ RESET_N pin reset

‒ Reset by power-on detection

‒ Reset by the watchdog timer (WDT) overflow

‒ Reset by RAM parity error (enable/disable can be selected)

‒ Reset by voltage level detection 0 (VLS0) (enable/disable can be selected)

‒ Reset by voltage level detection 1 (VLS1) (enable/disable can be selected)

‒ Reset by prohibition program address change

• Voltage level detect function

‒ 2 ch

‒ Threshold voltage: 12 values selectable

‒ Interrupt generation or reset generation can be selected

• Clock

‒ Low-speed clock

Internal low-speed RC oscillation (32.768 KHz)

‒ High-speed clock

PLL oscillation @ internal high-speed RC oscillation (32 MHz*1)

High-speed crystal oscillation (4 MHz)

PLL oscillation @ high-speed crystal oscillation (32 MHz*1*2)

‒ Selection of high-speed clock mode by software

PLL oscillation @ internal high-speed RC oscillation mode (16 MHz)

High-speed crystal oscillation mode (4 MHz)

PLL oscillation @ high-speed crystal oscillation mode (16 MHz)

The maximum frequency of the system clock is 16 MHz.

*

high-speed crystal (4 MHz).

• Power management

‒ HALT mode: Suspends the instruction execution by CPU (peripheral circuits are in operating states)

‒ STOP mode: Stops the low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are

stopped.)

‒ Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8, or 1/16 of the

oscillation clock)

‒ Block Control Function: Powers down (reset registers and stop clock supply) the circuits of unused function blocks