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ML9460 Datasheet(PDF) 3 Page - LAPIS Semiconductor Co., Ltd. |
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ML9460 Datasheet(HTML) 3 Page - LAPIS Semiconductor Co., Ltd. |
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3 / 27 page ![]() FEDL9460-01 LAPIS Semiconductor ML9460 3/27 Pin name I/O Polarity Descripiton Initial value Handling when not used Attribute Remarks DOC O Negative DISPOFF signal output pin Low — Digital See Sections 4.1.5, “Control Circuit,” and 4.2.3, “ DOC Signal Waveforms.” SHL I — Shift direction switching pin. Switches the shift direction of the shift register. Tied High or Low — Digital See Section 4.1.3, “Bidirectional Shift Register.” O1 to O240 O — Liquid crystal drive output pins. When the VDD voltage is input to the DSPOF pin, one of the three levels (V2, MV2, VC) is selected and output according to the combination of the FR signal and display data. — Pins that are made disabled by the SEL1 and SEL2 pins will output the nonselective level signal (VC). Analog See Section 4.1.1, “Liquid Crystal Drive Circuit.” Note: In the initial value column, - A dash “—” for an input pin indicates that the initial value is Don’t Care. - A dash “—” for an output pin indicates that the initial value is undefined. |
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