VCT3834A datasheet(49/172 Pages) MICRONAS

49 / 172 page

ADVANCE INFORMATION

VCT 38xxA

Micronas

Fig. 3–2: Memory environment of text controller

3.4. Teletext Acquisition

The only task of the slicer circuit is to extract teletext

lines from the incoming composite video signal and to

store them into the acquisition scratch buffer of the

internal/external SRAM. No page selection is done at

this hardware level.

Four analog sources can be connected, thus it is pos-

sible to receive text from one channel while watching

another on the screen. After clamping and AGC ampli-

fier the analog video signal is converted into binary

data. Sync separation is done by a sync slicer and a

horizontal PLL, which generate the horizontal and ver-

tical timing. By these means, no external sync signals

are needed and any available signal source can be

used for teletext reception.

The teletext information itself is acquired using adap-

tive slicers on bit and byte level with soft error detec-

tion to decrease the bit error rate under bad reception

conditions. The slicer can be programmed to different

bit rates for reception of PAL, NTSC or MAC world sys-

tem teletext as well as VPS, WSS, or CAPTION sig-

nals.

3.5. Teletext Page Management

As a state-of-the-art teletext decoder, the TPU is able

to store and manage a sufficient number of teletext

pages to absorb the annoying transmission cycle

times. The number of available pages is only limited by

the memory size. With an intelligent software and a

4-Mbit SRAM it is possible to store and to control more

than 500 teletext pages.

The management of such a data base is a typical soft-

ware task and is therefore performed by the 65C02.

Using a fixed length page table with one entry for every

possible page, the software distributes the content of

the acquisition scratch buffer among the page memory.

The page size is fixed to 1 kByte, only ghost rows are

chained in 128-Byte segments to avoid unused mem-

ory space.

A stored teletext page cannot be displayed directly,

because of the row-adaptive transmission and the

level 2 enhancements (row 26

−29). Therefore, the

CPU has to transfer the selected teletext page into a

display page buffer, adding extra data such as charac-

ter set extension and non-spacing attributes.

3.5.1. Memory Manager

The Memory manager is the core of the internal TPU

firmware. Most of the acquisition and display related

functions are controlled by this management.

Fig. 3–3: Memory Manager

DMA

Interface

12K

Program ROM

12K

Character ROM

Zero Page

Stack Page

I/O Page

ADR

DATA

RDY

65C02

BUSREQ

Display

DATA

ADR

Extra Page

8000

1000

0000

D000

Display

Memory

Manager

Display

Controller

Page

Memory

Page

Table

Scratch

Memory

Acquisition

VCT3834A Datasheet(PDF) 49 Page - Micronas

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