MF10 datasheet(15/20 Pages) NSC

15 / 20 page

30 Applications Information (Continued)

TLH10399 – 27

(a) Resistive Divider with

Decoupling Capacitor

TLH10399 – 28

(b) Voltage Regulator

TLH10399 – 29

with Divider

FIGURE 18 Three Ways of Generating

for Single-Supply Operation

32 SINGLE SUPPLY OPERATION

The MF10 can also operate with a single-ended power sup-

ply

Figure 17 shows the example filter with a single-ended

power supply VAa and VDa are again connected to the

positive power supply (8V to 14V) and VAb and VDb are

connected to ground The AGND pin must be tied to Va 2

for single supply operation This half-supply point should be

very ‘‘clean’’ as any noise appearing on it will be treated as

an input to the filter It can be derived from the supply volt-

age with a pair of resistors and a bypass capacitor

(Figure

18a) or a low-impedance half-supply voltage can be made

using a three-terminal voltage regulator or an operational

amplifier

(Figures 18b and 18c) The passive resistor divider

with a bypass capacitor is sufficient for many applications

provided that the time constant is long enough to reject any

power supply noise It is also important that the half-supply

reference present a low impedance to the clock frequency

so at very low clock frequencies the regulator or op-amp

approaches may be preferable because they will require

smaller capacitors to filter the clock frequency The main

power supply voltage should be clean (preferably regulated)

and bypassed with 01 mF

33 DYNAMIC CONSIDERATIONS

The maximum signal handling capability of the MF10 like

that of any active filter is limited by the power supply volt-

ages used The amplifiers in the MF10 are able to swing to

within about 1V of the supplies so the input signals must be

kept small enough that none of the outputs will exceed

these limits If the MF10 is operating on g5V for example

the outputs will clip at about 8 Vp–p The maximum input

voltage multiplied by the filter gain should therefore be less

than 8 Vp–p

Note that if the filter Q is high the gain at the lowpass or

highpass outputs will be much greater than the nominal filter

gain

(Figure 6) As an example a lowpass filter withaQof

10 will have a 20 dB peak in its amplitude response at fO If

the nominal gain of the filter HOLP is equal to 1 the gain at

fO will be 10 The maximum input signal at fO must therefore

be less than 800 mVp–p when the circuit is operated on

5V supplies

Also note that one output can have a reasonable small volt-

age on it while another is saturated This is most likely for a

circuit such as the notch in Mode 1

(Figure 7) The notch

output will be very small at fO so it might appear safe to

apply a large signal to the input However the bandpass will

have its maximum gain at fO and can clip if overdriven If

one output clips the performance at the other outputs will

be degraded so avoid overdriving any filter section even

ones whose outputs are not being directly used Accompa-

nying

Figures 7 through 15 are equations labeled ‘‘circuit

dynamics’’ which relate the Q and the gains at the various

outputs These should be consulted to determine peak cir-

cuit gains and maximum allowable signals for a given appli-

cation

34 OFFSET VOLTAGE

The MF10’s switched capacitor integrators have a higher

equivalent input offset voltage than would be found in a

typical continuous-time active filter integrator

Figure 19

shows an equivalent circuit of the MF10 from which the out-

put DC offsets can be calculated Typical values for these

offsets with SAB tied to Va are

Vos1 e opamp offset e g5mV

Vos2 eb150 mV

501

300 mV

1001

Vos3 eb70 mV

501

140 mV

1001

When SAB is tied to Vb Vos2 will approximately halve The

DC offset at the BP output is equal to the input offset of the

lowpass integrator (Vos3) The offsets at the other outputs

depend on the mode of operation and the resistor ratios as

described in the following expressions

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