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30 Applications Information (Continued)

For most applications the outputs are AC coupled and DC

offsets are not bothersome unless large signals are applied

to the filter input However larger offset voltages will cause

clipping to occur at lower AC signal levels and clipping at

any of the outputs will cause gain nonlinearities and will

change fO and Q When operating in Mode 3 offsets can

become excessively large if R2 and R4 are used to make

fCLK fO significantly higher than the nominal value espe-

cially if Q is also high An extreme example is a bandpass

filter having unity gain aQof20 and fCLK fO e 250 with

pin 12 tied to ground (1001 nominal) R4R2 will therefore

be equal to 625 and the offset voltage at the lowpass out-

put will be about a1V Where necessary the offset voltage

can be adjusted by using the circuit of

Figure 20 This allows

adjustment of VOS1 which will have varying effects on the

different outputs as described in the above equations Some

outputs cannot be adjusted this way in some modes how-

ever (VOS(BP) in modes 1a and 3 for example)

35 SAMPLED DATA SYSTEM CONSIDERATIONS

The MF10 is a sampled data filter and as such differs in

many ways from conventional continuous-time filters An im-

portant characteristic of sampled-data systems is their ef-

fect on signals at frequencies greater than one-half the

sampling frequency (The MF10’s sampling frequency is the

same as its clock frequency) If a signal with a frequency

greater than one-half the sampling frequency is applied to

the input of a sampled data system it will be ‘‘reflected’’ to

a frequency less than one-half the sampling frequency

Thus an input signal whose frequency is fs 2 a 100 Hz will

cause the system to respond as though the input frequency

was fs 2 b 100 Hz This phenomenon is known as ‘‘alias-

ing’’ and can be reduced or eliminated by limiting the input

signal spectrum to less than fs 2 This may in some cases

require the use of a bandwidth-limiting filter ahead of the

MF10 to limit the input spectrum However since the clock

frequency is much higher than the center frequency this will

often not be necessary

Another characteristic of sampled-data circuits is that the

output signal changes amplitude once every sampling peri-

od resulting in ‘‘steps’’ in the output voltage which occur at

the clock rate

(Figure 21)

If necessary these can be

‘‘smoothed’’ with a simple R – C low-pass filter at the MF10

output

The ratio of fCLK to fC (normally either 501 or 1001) will

also affect performance A ratio of 1001 will reduce any

aliasing problems and is usually recommended for wide-

band input signals In noise sensitive applications however

a ratio of 501 may be better as it will result in 3 dB lower

output noise The 501 ratio also results in lower DC offset

voltages as discussed in Section 34

The accuracy of the fCLK fO ratio is dependent on the value

of Q This is illustrated in the curves under the heading

‘‘Typical Performance Characteristics’’ As Q is changed

the true value of the ratio changes as well Unless the Q is

low the error in fCLK fO will be small If the error is too large

for a specific application use a mode that allows adjustment

of the ratio with external resistors

It should also be noted that the product of Q and fO should

be limited to 300 kHz when fO k 5 kHz and to 200 kHz for

fO l 5 kHz

TLH10399 – 32

FIGURE 21 The Sampled-Data Output Waveform

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