AD5162 datasheet(16/20 Pages) AD

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AD5162

Rev. A | Page 16 of 20

SPI INTERFACE

SPI COMPATIBLE 3-WIRE SERIAL BUS

The AD5162 contains a 3-wire SPI compatible digital interface

(SDI, CS, and CLK). The 9-bit serial word must be loaded MSB

first. The format of the word is shown in Table 8.

The positive-edge sensitive CLK input requires clean transitions

to avoid clocking incorrect data into the serial input register.

Standard logic families work well. If mechanical switches are

used for product evaluation, they should be debounced by a

flip-flop or other suitable means. When CS is low, the clock

loads data into the serial register on each positive clock edge

(see Figure 42).

The data setup and data hold times in the specification table

determine the valid timing requirements. The AD5162 uses a

9-bit serial input data register word that is transferred to the

internal RDAC register when the CS line returns to logic high.

Extra MSB bits are ignored.

Table 8. Serial Data-Word Format

MSB

LSB

SDI

CLK

VOUT

RDAC REGISTER LOAD

Figure 42. SPI Interface Timing Diagram

(VA = 5 V, VB = 0 V, VW = VOUT

)

tCSHO

tCSS

tCL

tCH

tDS

tCSW

tCS1

tCSH1

tCH

CLK

VOUT

VDD

±1LSB

SDI

(DATA IN)

Figure 43. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT

)

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