AM29LV640MU datasheet(22/58 Pages) AMD

22 / 58 page

June 12, 2003

Am29LV640MU

AD V A NCE

INF O R M A T IO N

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h, any time the device is ready to read array data.

The system can read CFI information at the addresses

given in Tables 6–9. To terminate reading CFI data,

the system must write the reset command.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 6–9. The

system must write the reset command to return the de-

vice to reading array data.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the

World Wide Web at http://www.amd.com/flash/cfi. Al-

ternatively, contact an AMD representative for copies

of these documents.

Table 6.

CFI Query Identification String

Table 7.

System Interface String

Addresses (x16)

Data

Description

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

0002h

0000h

Primary OEM Command Set

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

19h

1Ah

0000h

Address for Alternate OEM Extended Table (00h = none exists)

Addresses (x16)

Data

Description

1Bh

0027h

CC Min. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch

0036h

CC Max. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Dh

0000h

VPP Min. voltage (00h = no VPP pin present)

1Eh

0000h

VPP Max. voltage (00h = no VPP pin present)

1Fh

0007h

Typical timeout per single word write 2

N µs

20h

0007h

Typical timeout for Min. size buffer write 2

N µs (00h = not supported)

21h

000Ah

Typical timeout per individual block erase 2

N ms

22h

0000h

Typical timeout for full chip erase 2

N ms (00h = not supported)

23h

0001h

Max. timeout for word write 2

N times typical

24h

0005h

Max. timeout for buffer write 2

N times typical

25h

0004h

Max. timeout per individual block erase 2

N times typical

26h

0000h

Max. timeout for full chip erase 2

N times typical (00h = not supported)

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