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SiP32449 Datasheet(PDF) 5 Page - Vishay Siliconix

Part # SiP32449
Description  1.7 V to 5.5 V, 3 A Load Switch with Negative VIN Tolerance
PDF  12 Pages
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Manufacturer  VISHAY [Vishay Siliconix]
Direct Link  http://www.vishay.com
Logo VISHAY - Vishay Siliconix

SiP32449 Datasheet(HTML) 5 Page - Vishay Siliconix

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SiP32448, SiP32449
www.vishay.com
Vishay Siliconix
S15-1920-Rev. C, 24-Aug-15
5
Document Number: 62959
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
In order to calculate the maximum allowed DC current the
switch
RDS(on)
temperature
dependency
should
be
considered.
As an example let us calculate maximum load current
at TA = 70 °C and input voltage of 1.8 V. At this input voltage
the RDS(on) at 25 °C 43 m (see specification table). The
RDS(on) at 125 °C can be extrapolated from this data using
the following formula:
Where TC is the RDS(on) temperature coefficient expressed in
percent change per degree C.
For SiP32448 the approximated value is 0.31 %/°C. TJ max.
is the maximum allowed junction temperature (125 °C).
Therefore,
The maximum current limit is then determined by
Which in this case is 2.38 A.
Due to device limitation the max switch DC current
should exceed 3 A in any condition.
To obtain the highest power dissipation the power pad of
the device should be connected to a heat sink on the printed
circuit board. Figure 4 shows a typical PCB layout. All
copper traces and vias for the VIN and VOUT pins should be
sized adequately to carry the maximum continuous current.
Negative Input Voltage
The SiP32448 and SiP32449 can withstand maximum
negative 2 V at its input due to any spike from abnormal or
fault condition of the system.
Recommended Board Layout
For improved performance, all traces should be as short as
possible to minimize stray inductances and parasitic effects.
The input and output capacitors should be kept as close
as possible to the input and output pins respectively.
Connecting the central exposed pad to GND, using wide
traces for input, output, and GND help reducing the case to
ambient thermal impedance. See fig. 4.
BOARD LAYOUT
Fig. 4 - Recommended Board Layout
TYPICAL APPLICATION SCHEMATIC
Fig. 5 - Application Schematic
RDS(on)_125 °C = RDS(on)_25 °C x (1 + TC x (TJ max. - 25)/100 )
RDS(on) (at 125 °C) =
43 m
Ω x (1 + 0.31 x (125 - 25)/100 ) ≈ 57 mΩ
)
(
(max.)
(max.)
on
DS
LOAD
R
P
I
<



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