MPC8240 datasheet(22/52 Pages) MOTOROLA

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MPC8240 Integrated Processor Hardware Specifications

MOTOROLA

Electrical and Thermal Characteristics

Figure 13 through Figure 16 show I2C timings.

Figure 13. I2C Timing Diagram I

Figure 14. I2C Timing Diagram II

Stop condition setup time

4.0

—

CLKs

1, 2

Notes:

1. Units for these specifications are in SDRAM_CLK units.

2. The actual values depend on the setting of the digital filter frequency sampling rate (DFFSR) bits in the frequency

divider register I2CFDR. Therefore, the noted timings in this table are all relative to qualified signals. The qualified

SCL and SDA are delayed signals from what is seen in real time on the I2C bus. The qualified SCL and SDA signals

are delayed by the SDRAM_CLK clock times DFFSR times two plus one SDRAM_CLK clock. The resulting delay

value is added to the value in the table (where this note is referenced). See Figure 14.

3. Since SCL and SDA are open-drain type outputs, which the MPC8240 can only drive low, the time required for SCL

or SDA to reach a high level depends on external signal capacitance and pull-up resistor values.

4. Specified at a nominal 50-pF load.

5. DFDR is the decimal divider number indexed by the value of FDR[5:0]. Refer to the I

2C Interface chapter’s serial bit

clock frequency divider selections table. FDR[n] refers to the frequency divider register I2CFDR bit n. N is equal to

a variable number that would make the result of the divide (data hold time value) equal to a number less than 16.

M is equal to a variable number that would make the result of the divide (data hold time value) equal to a number

less than 9.

Table 13. I2C Output AC Timing Specifications (continued)

At recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V

Num

Characteristic

Min

Max

Unit

Notes

SCL

SDA

SCL

SDA

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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