PC87360 datasheet(3/168 Pages) NSC

3 / 168 page

Features (Continued)

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— Can be customized by using the PC87323, which in-

cludes a RAM-based KBC as a development plat-

form for KBC code

• ACCESS.bus Interface (ACB)

— Serial interface compatible with SMbus physical layer

— Compatible with Philips’ I2C®

— ACB master and slave

— Supports polling and interrupt controlled operation

— Optional internal pull-up on SDA and SCL pins

• WATCHDOG Timer

— Times out the system based on user-programmable

time-out period

— System power-down capability for power saving

— User-deﬁned trigger events to restart WATCHDOG

— Optional routing of WATCHDOG output on IRQ

and/or SMI lines

• System Wake-Up Control (SWC)

— Power-up request upon detection of Keyboard,

Mouse, RI1, RI2, RING activity and General-Pur-

pose Input Events, as follows:

Preprogrammed Keyboard or Mouse sequence

External modem ring on serial port

Ring pulse or pulse train on the RING input signal

Preprogrammed CEIR address in a preselected

standard (NEC, RCA or RC-5)

General-Purpose Input Events

IRQs of internal logical devices

— Optional routing of power-up request on IRQ and/or

SMI lines

— Battery-backed event conﬁguration

— Programmable VSB-powered output for blinking

LEDs (LED1, LED2) control

• Clock Sources

— 48 MHz clock input

— LPC clock, up to 33 MHz

— On-chip low frequency clock generator for wake-up

• Power Supplies

— 3.3V supply operation

— Main (VDD)

— Standby (VSB)

— Battery backup (VBAT)

— All pins are 5V tolerant and back-drive protected, ex-

cept LPC bus pins

• Strap Configuration

— Base Address (BADDR) strap to determine the base

address of the Index-Data register pair

— Test strap to force the device into test mode (re-

served for National Semiconductor use)

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