PC87360 datasheet(5/168 Pages) NSC

5 / 168 page

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Table of Contents

Datasheet Revision Record .................................................................................................................... 4

1.0

Signal/Pin Connection and Description

1.1

CONNECTION DIAGRAM ......................................................................................................... 12

1.2

BUFFER TYPES AND SIGNAL/PIN DIRECTORY .................................................................... 13

1.3

PIN MULTIPLEXING ................................................................................................................. 17

1.4

DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................ 19

1.4.1

ACCESS.bus Interface (ACB) .................................................................................... 19

1.4.2

Bus Interface ............................................................................................................... 19

1.4.3

Clock ............................................................................................................................ 19

1.4.4

Fan Speed Control and Monitor (FSCM) ..................................................................... 19

1.4.5

Floppy Disk Controller (FDC) ...................................................................................... 20

1.4.6

General-Purpose Input/Output (GPIO) Ports ............................................................... 21

1.4.7

Infrared (IR) ................................................................................................................. 21

1.4.8

Keyboard and Mouse Controller (KBC)

..................................................................... 22

1.4.9

Parallel Port

............................................................................................................... 22

1.4.10

Power and Ground ..................................................................................................... 23

1.4.11

Protection .................................................................................................................... 24

1.4.12

Serial Port 1 and Serial Port 2 ..................................................................................... 24

1.4.13

Strap Configuration ...................................................................................................... 25

1.4.14

System Wake-Up Control ............................................................................................ 25

1.4.15

WATCHDOG Timer (WDT) ......................................................................................... 25

1.5

INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................ 26

2.0

Device Architecture and Configuration

2.1

OVERVIEW ............................................................................................................................... 29

2.2

CONFIGURATION STRUCTURE AND ACCESS ..................................................................... 29

2.2.1

The Index-Data Register Pair ...................................................................................... 29

2.2.2

Banked Logical Device Registers Structure ................................................................ 31

2.2.3

Standard Logical Device Configuration Register Definitions ....................................... 32

2.2.4

Standard Configuration Registers ............................................................................... 34

SuperI/O Control and Configuration Registers ............................................................ 34

Logical Device Control and Configuration Registers ................................................... 34

Control .........................................................................................................................35

Standard Configuration ................................................................................................ 35

Special Configuration .................................................................................................. 35

2.2.5

Default Configuration Setup ........................................................................................ 35

2.2.6

Power States ...............................................................................................................35

2.2.7

Address Decoding ....................................................................................................... 36

2.3

INTERRUPT SERIALIZER ........................................................................................................ 36

2.4

PROTECTION ........................................................................................................................... 37

2.4.1

Access Lock to I/O Ports ............................................................................................. 37

2.4.2

Pin Configuration Lock ................................................................................................ 37

2.4.3

GPIO Pin Function Lock .............................................................................................. 37

PC87360 Datasheet(PDF) 5 Page - National Semiconductor (TI)

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