PCM16C00 datasheet(19/40 Pages) NSC

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50 Functional Description (Continued)

534 Bus Arbitration

National’s PCM16C00 IC supports a bus arbitration unit that

may arbitrate three possible masters They are the PCMCIA

Host Function 0 or Function 1 There are 4 external pins

and 2 internal pins for enforcing arbitration decisions These

are BREQ(10) BACK(10) HBREQ and HBACK As de-

scribed in the registers section a priority arbitration policy is

used

Each of the three masters may be programmed with a priori-

ty from the set (0123) independently of the other masters

priority A value of 3 is the highest priority the value 0 is the

lowest In addition to this there is also a programmable 8-bit

latency timer to guarantee a certain bus ownership time in

clocks If the value is 0 the PCM16C00 arbiter will follow the

priority policy strictly Here a higher priority unit may pre-

empt a lower priority unit by removing its BACK

A lower

priority and equivalent priority unit may not be granted the

card-side local bus until the higher priority unit is complete

When the latency timer has a finite value (ie 32) a higher

priority unit may not be pre-empted from the bus by lower

priority units The difference is that a unit may be pre-empt-

ed by higher or equivalent priority units but not until the

latency timer expires This guarantees the unit a certain bus

time and improves efficiency in high bus traffic systems The

latency timer does not begin counting down until another

unit vies for the bus

If a round-robin arbitration policy is desired all three units

may be set to the same priority with a finite value in the

latency timer Here any unit may be granted the bus and

control it until another unit requires the bus At that time the

first unit has it until the latency expires and it is removed

from the bus (BACK( )

de-asserted) The second unit is

granted the bus by having its BACK( )

asserted

Note

The destination of a PCMCIA host access (either to function 0 or 1) is

implicit in the address and which IO window it falls within This steer-

ing does not require arbitration however it requires that the PCMCIA

host is granted access to the card local bus

535 Common Memory Management

National’s PCM16C00 has features built in for using a

shared common memory architecture on the card This is

useful for functions such as an Ethernet LAN especially

those using a shared memory address space for the packet

data area in which the card’s local RAM is mapped into the

system memory address space Using this feature access

to common memory may be granted to either the PCMCIA

host or to one of the external functions

For the PCMCIA host to access the common memory all

that is required is for a PCMCIA Common Memory transac-

tion and bus ownership granted by the PCM16C00 Arbiter

The PCM16C00 will perform the PCMCIA requested access

There is no decoding internal to the device to set up Com-

mon Memory Windows Simple decoding can be done exter-

nal to the PCM16C00 using address lines For proper data

steering and memory readwrite strobing the PCM16C00

will check the state of the Memls8 bit in the Pin Polarity

If a function desires to access common memory it requires

that it first arbitrate and win the card-side bus If the LAN

Mode bit is clear in Function Configuration Option Register

the PCM16C00 will TRI-STATE MEMWEH

and

MEMWEL

any time function 0 or function 1 is granted the

bus When the LAN Mode bit is set the IC will TRI-STATE

MEMWEH

and MEMWEL

when function 1 is granted

the bus

The PCM16C00 will drive MEMWEH

and

MEMWEL

when function 0 is granted the bus In this case

MEMWEH

andor MEMWEL

will be strobed based on

MEMWR

being strobed by the LAN The Memls8 bit in the

Pin Polarity Register will be checked to determine strobing

In all cases any time a function is granted the bus the

PCM16C00 will TRI-STATE the MEMOE

signal to allow

the bus mastering function to read from the memory For

this scheme to work each function must TRI-STATE its re-

spective memory write strobe when it is not granted the bus

and must connect its read strobe to the MEMOE

signal

Pull-up resistors on the PCM16C00’s MEMOE

output and

MEMWR

input will maintain a high level to prevent glitch-

ing during bus arbitration

While the PCM16C00 will pass any Common Memory ac-

cess to the 64 Mbyte of common memory space common

memory may be fractured into two ranges if desired It will

use one address line to select either the shared SRAM de-

scribed above or another common memory device

60 Operational Modes

61 INITIAL SETUP (RESET) AND CONFIGURATION

In order to set up the IO windows the Function Base Reg-

isters 0 1 and the Function Limit Registers 0 1 must be

loaded These registers are loaded with base address infor-

mation gained from reading the TPCE

IO field within the

Card Configuration Table Entry Tuple (CISTPL

CFTA-

BLE

ENTRY 1Bh) in the CIS (Card Information Structure)

This will allow the system software to configure the windows

and set the IO addresses for each function The software

locates the Configuration Option Registers based on ad-

dress offset values stored in the TPCC

RADR field within

the Configuration Tuple (CISTPL

CONFIG 1Ah) in the

CIS Upon a subsequent readwrite operation from the

PCMCIA host to the current IO window address the

PCM16C00 decodes for a match and then passes the ap-

propriate data address and control signals to the appropri-

ate function port Note the Attribute memory CIS is initially

loaded from the EEPROM upon reset

62 RESET CONDITIONS

When the device is reset using the reset pin the following

actions take place First the attribute memory CIS is re-

loaded from the EEPROM The Function Configuration Op-

tion Registers 0 1 are reset to a value of 00 Hex All other

registers are set to their default values

63 INTERRUPT CONTROL

For multi-function operation the PCM16C00 implements a

shared interrupt scheme

The PCM16C00 will assert

PCMCIA IREQ

when either CINT(0) or CINT(1) is assert-

ed If the Function Configuration Option Register is config-

ured for pulsed mode interrupts the IREQ

pin will send

out a pulse width of period 16fMCLK(0) During multi-func-

tion operation however level mode interrupts are strongly

recommended The Function Configuration Status Registers

indicate which function initiated the interrupt and interrupts

will continue until the interrupt requests are processed This

mode would be used if both functions are running at the

same time (concurrently)

See the description of the IntrReset bit in the Function Con-

figuration Status Registers 0 1 for a multi-function interrupt

protocol that insures multiple interrupts sharing one IREQ

line are not missed

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