DocID029823 Rev 1

11/18

UM2120

Getting started

18

3.1.4

EVALSTGAP1AS default parameters



IN-/DIAG2 configured as input



Active Miller clamp enabled





VDD OVLO function enabled



Thermal shutdown protection enabled



The DIAG1 pin reports the following faults event:

–

DESAT events

–

VDD supply failures

–Missing VH

–

Thermal shutdown

–

Register error R and L



All others features are disabled

3.2

Using EVALSTGAP1AS with STEVAL-PCC009V2 and

STGAP1AS evaluation software

Using the EVALSTGAP1AS board in connection with the 'STGAP1AS evaluation software'

and the STEVAL-PCC009V2 interface board it is possible to evaluate the device

functionalities and driving two EVALSTGAP1AS boards implementing independent, half

bridge, or interleaved configuration of power switches.

The software allows saving the device parameters configuration in a dedicated file that can

be reloaded whenever it is necessary, for example after the board power-on. The 'Save' and

'Load' buttons on the bottom-left side of the STGAP1AS configuration panel (Figure 10)

have these functions.

3.2.1

Check list





EVALSTGAP1AS board



STEVAL-PCC009V2 interface board



STGAP1AS evaluation software (the right version for your OS)



Power supply



PWM function generator



10-pin flat cable and USB - MiniUSB cable

3.2.2

Single EVALSTGAP1AS board setup example

1.

VDD = 3.3 V from the STEVAL-PCC009V2: closing JP4 and JP6

2.

VH from external power supply (J2 connector)

3.

VL = GNDISO (JP5 closed)

4.

PWM input signals can be applied to the J3 connector (IN-, IN+)