SCANPSC110FDMQB datasheet(4/29 Pages) NSC

4 / 29 page

Table of Contents (Continued)

TABLE 2. Detailed Pin Description Table (Continued)

Pin #

Name

I/O (Note 1)

(SOIC

Description

& LCC)

GND

Ground potential

14, 21

Power supply pins 0V.

Note 1: All pins are active HIGH unless otherwise noted.

Overview of SCANPSC110F Bridge Functions

SCANPSC110F BRIDGE ARCHITECTURE

Figure 1 shows the basic architecture of the ’PSC110F. The

device’s major functional blocks are illustrated here. The

TAP Controller, a 16-state state machine, is the central con-

trol for the device. The instruction register and various test

data registers can be scanned to exercise the various func-

tions of the ’PSC110F (these registers behave as defined in

IEEE Std. 1149.1).

The ’PSC110F selection controller provides the functionality

that allows the 1149.1 protocol to be used in a multi-drop en-

vironment. It primarily compares the address input to the slot

identification and enables the ’PSC110F for subsequent

scan operations.

The Local Scan Port Network (LSPN) contains multiplexing

logic used to select different port configurations. The LSPN

control block contains the Local Scan Port Controllers

(LSPC) for each Local Scan Port (LSP

1, LSP2, and LSP3).

This control block receives input from the ’PSC110F instruc-

tion register, mode register, and the TAP controller. Each lo-

cal port contains all four (4) boundary scan signals needed to

interface with the local TAPs.

SCANPSC110F BRIDGE STATE MACHINES

The ’PSC110F is IEEE 1149.1-compatible, in that it supports

all required 1149.1 operations. In addition, it supports a

higher level of protocol, (Level 1), that extends the IEEE

1149.1 Std. to a multi-drop environment.

DS100327-3

FIGURE 1. SCANPSC110F Bridge Architecture

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