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SCANPSC110FDMQB Datasheet(PDF) 14 Page - National Semiconductor (TI) |
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SCANPSC110FDMQB Datasheet(HTML) 14 Page - National Semiconductor (TI) |
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14 / 29 page  Level 2 Protocol (Continued) Register Descriptions Instruction Register The instruction shift register is an 8-bit register that is in se- ries with the scan chain whenever the TAP Controller of the SCANPSC110F Bridge is in the Shift-IR state. Upon exiting the Capture-IR state, the value “XXXXXX01” is captured into the instruction register, where “XXXXXX” represents the value on the S (0–5) inputs. When the ’PSC110F controller is in the Wait-For-Address state, the instruction register is used for ’PSC110F selection via address matching. In addressing individual ’PSC110Fs, the chip’s addressing logic performs a comparison between a statically-configured (hard-wired) value on that ’PSC110F’s slot inputs, and an address which is scanned into the chip”s instruction register. Binary address codes “000000” through “111010” (“00” through “3A” Hex) are reserved for address- ing individual ’PSC110Fs. Address “3B” Hex is for Broadcast mode. In doing multi-cast (group) addressing, a scanned-in address is compared against the (previously scanned-in) contents of a ’PSC110F’s Multi-Cast Group register. Binary address codes “111110” through “111111” (“3A” through “3F” Hex) are reserved for multi-cast addressing, and should not be as- signed as ’PSC110F slot-input values. Boundary-Scan Register The boundary-scan register is a “sample only” shift register containing cells from the S (0–5) and OE inputs. The register allows testing of circuitry external to the ’PSC110F. It permits the signals flowing between the system pins to be sampled and examined without interfering with the operation of the on-chip system logic. The scan chain is arranged as follows: TDI B→OE →S5→S4→ S 3 →S2→S1→S0→LSPN→TDOB Bypass Register The bypass register is a 1-bit register that operates as speci- fied in IEEE Std. 1149.1 once the ’PSC110F has been se- lected. The register provides a minimum length serial path for the movement of test data between TDI B and the LSPN. This path can be selected when no other test data register needs to be accessed during a board-level test operation. Use of the bypass register shortens the serial access-path to test data registers located in other components on a board-level test data path. Multi-Cast Group Register “Multi-cast” is a method of simultaneously communicating with more than one selected ’PSC110F. The multi-cast group register (MCGR) is a 2-bit register used to determine which multi-cast group a particular ’PSC110F is assigned to. Four addresses are reserved for multi-cast ad- dressing. When a ’PSC110F is in the Wait-For-Address state and receives a multi-cast address, and if that ’PSC110F’s MCGR contains a matching value for that multi-cast ad- dress, the ’PSC110F becomes selected and is ready to re- ceive Level 2 Protocol (i.e., further instructions). The MCGR is initialized to “00” upon entering the Test-Logic-Reset state. The following actions are used to perform multi-cast ad- dressing: 1. Assign all target ’PSC110Fs to a multi-cast group by writing each individual target ’PSC110F’s MCGR with the same multi-cast group code (see Table 6). This con- figuration step must be done by individually addressing each target ’PSC110F, using that chip’s assigned slot value. 2. Scan out the multi-cast group address through the TDI B input of all ’PSC110Fs. Note that this occurs in parallel, resulting in the selection of only those ’PSC110Fs whose MCGR was previously programmed with the matching multi-cast group code. TABLE 6. Multi-Cast Group Register Addressing MCGR Hex Address Binary Address Bits 1, 0 00 3C XX111100 01 3D XX111101 10 3E XX111110 11 3F XX111111 DS100327-11 FIGURE 10. Local Scan Port Synchronization from Parked-RTI State www.national.com 14 |
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