SCANPSC110FDMQB datasheet(13/29 Pages) NSC

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Level 2 Protocol (Continued)

one of the TAP Controller pause states. A local port does not

become parked until the ’PSC110F’s TAP Controller is se-

quenced through

Exit1-DR/IR into the Update-DR/IR state.

When the ’PSC110F TAP Controller is in the

Exit1-DR or

Exit1-IRstate and TMS

B is high, the LSP controller forces a

constant logic “0” onto TMS

L thereby parking the port in the

Pause-DR or Pause-IR state respectively (see Figure 4 ).

Another instruction can then be loaded to reconfigure the lo-

cal ports or to deselect the ’PSC110F (i.e.,

MODESEL, GO-

TOWAIT, etc.).

If the

PARKPAUSE instruction is given to a bridge whose

LSPs are parked in

Pause-IR or Pause-DR, the parked LSPs

will become unparked when the ’PSC110F’s TAP controller

is sequenced into the respective Pause state.

The

PARKPAUSE instruction was implemented with this

dual functionality to enable backplane testing (interconnect

testing between boards) with simultaneous Updates and

Captures.

Simultaneous Update and Capture of several boards can be

performed by parking LSPs of the different boards in the

Pause-DR TAP controller state, after shifting the data to be

updated into the boundary registers of the components on

each board. The broadcast address is used to select all

’PSC110Fs connected to the backplane. The

PARKPAUSE

instruction is scanned into the selected ’PSC110Fs and the

’PSC110F TAP controllers are sequenced to the

Pause-DR

state where the LSPs of all ’PSC110Fs become unparked.

The local TAP controllers are then sequenced through the

Update-DR, Select-DR, Capture-DR, Exit1-DR, and parked

in the Pause-DR state, as the ’PSC110F TAP controller is se-

quenced into the Update-DR state. When a LSP is parked, it

is removed from the active scan chain.

GOTOWAIT: This instruction is used to return all ’PSC110Fs

to the

Wait-For-Address state. All unparked LSPs will be

parked in the

Test-Logic-Reset TAP controller state (see Fig-

ure 5 ).

MODESEL: The MODESEL instruction inserts the mode

mines the LSPN configuration. Bit 7 of the mode register is a

read-only counter status flag.

MCGRSEL: This instruction inserts the multi-cast group reg-

ister (MCGR) into the active scan chain. The MCGR is used

to group ’PSC110Fs into multi-cast groups for parallel TAP

sequencing (i.e., to simultaneously perform identical scan

operations).

SOFTRESET: This instruction causes all 3 Port configura-

tion controllers (

Figure 4) to enter the Parked-TLR state,

which forces TMS

Ln high; this parks each local port in the

Test-Logic-Reset state within 5 TCK

B cycles.

LFSRSEL: This instruction inserts the linear feedback shift

pacted signature to be shifted out of the LFSR during the

Shift-DR state. (The signature is assumed to have been

computed during earlier

LFSRON shift operations.) This in-

struction disables the LFSR register’s feedback circuitry,

turning the LFSR into a standard 16-bit shift register. This al-

lows a signature to be shifted out of the register, or a seed

value to be shifted into it.

LFSRON: Once this instruction is executed, the linear feed-

back shift register samples data from the active scan path

(including all unparked TDI

Ln) during the Shift-DR state.

Data from the scan path is shifted into the linear feedback

shift register and compacted. This allows a serial stream of

data to be compressed into a 16-bit signature that can sub-

sequently be shifted out using the

LFSRSEL instruction. The

linear feedback shift register is not placed in the scan chain

during this mode. Instead, the register samples the active

scan-chain data as it flows from the LSPN to TDO

LFSROFF: This instruction terminates linear feedback shift

ceiving this instruction.

CNTRSEL: This instruction inserts the 32-bit TCK counter

shift register into the active scan chain. This allows the user

to program the number of “n” TCK cycles to send to the

parked local ports once the

CNTRON instruction is issued

(e.g., for BIST operations). Note that to ensure completion of

count-down, the ’PSC110F should receive at least “n” TCK

pulses.

CNTRON: This instruction enables the TCK counter. The

counter begins counting down on the first rising edge of

TCK

B following the Update-IR TAP controller state and is

decremented on each rising edge of TCK

B thereafter. When

the TCK counter reaches terminal count, “00000000” Hex,

TCK

L of all parked LSP’s is held low. The CNTROFF in-

struction must be issued before unparking the LSPs of a

’PSC110F whose counter has reached terminal count.

This function over-rides the mode register TCK control bit

(bit-3).

CNTROFF: This instruction disables the TCK counter, and

TCK

L control is returned to the mode register (bit-3).

DS100327-10

FIGURE 9. Local Scan Port Synchronization from

Parked-TLR Instruction

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