L6718 datasheet(67/71 Pages) STMICROELECTRONICS

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L6718

Layout guidelines

The layout is one of the most important factors to consider when designing high-current

applications. A good layout solution can generate benefits by lowering power dissipation on

the power paths; reducing radiation and a proper connection between signal and power

ground can optimize the performance of the control loops.

Two kinds of critical components and connections must be considered when laying out a

VRM based on the L6718: power components and connections and small signal component

connections.

14.1

Power components and connections

These are the components and connections where switching and high continuous current

flows from the input to the load. The first priority when placing components must be

reserved for this power section, minimizing the length of each connection and loop as much

as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections

must be part of a power plane and realized by wide and thick copper traces: loop must be

minimized. The critical components, i.e. the power transistors, must be close to one another.

The use of a multi-layer printed circuit board is recommended.

As the L6718 uses external drivers to switch the Power MOSFETs, check the selected driver

documentation for information related to the proper layout for this part.

14.2

Small signal components and connections

These are small signal components and connections to critical nodes of the application as

well as bypass capacitors for the device supply. Locate the bypass capacitor close to the

device and refer sensitive components such as the frequency set-up resistor ROSC (both

sections). The VSEN and SVSEN pins filtered vs. GND helps to reduce noise injection into

the device and the ENABLE pin filtered vs. GND helps to reduce false tripping due to

coupled noise: take care when routing the driving net for this pin in order to minimize

coupled noise.

Remote buffer connection must be routed as parallel nets from the VSEN/FBG and

SVSEN/SFBG pins to the load in order to avoid the pick-up of any common mode noise.

Connecting these pins in points far from the load causes a non-optimum load regulation,

increasing output tolerance.

Locate current reading components close to the device. The PCB traces connecting the

reading points must use dedicated nets, routed as parallel traces in order to avoid the pick-

up of any common mode noise. It's also important to avoid any offset in the measurement

and, to get a better precision, to connect the traces as close as possible to the sensing

elements. Symmetrical layout is also suggested. A small filtering capacitor can be added,

near the controller, between VOUT and GND, on the CSx-line when reading across the

inductor to allow higher layout flexibility.

L6718 Datasheet(PDF) 67 Page - STMicroelectronics

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