L6718 datasheet(42/71 Pages) STMICROELECTRONICS

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L6718 power manager

L6718

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L6718 power manager

The L6718 power manager, configured by pins CONFIG2/SCL and CONFIG3/SDA,

provides a large number of configuration settings and monitoring to increase the

performance of both rails of the step-down DC-DC voltage regulator.

These pins can be configured in 2 different modes by setting ON/OFF the SMBus by

CONFIG0 pinstrapping (see Section 6.6.1 and Section 6.6.2 for details).

–

SCL and SDA (if SMBus is set ON): power management is provided from a master

with SMBus communication interface through two-wire clock (SCL) and data

(SDA) which guarantee a high level programmability (setting and monitoring) while

the system is running.

–

CONFIG2 and CONFIG 3 (if SMBus is set OFF): power management is provided

with 2 pinstrappings set during the startup (see Section 6.6.5 and Section 6.6.6 for

details).

7.1

SMBus power manager

The SMBus interface is set by CONFIG0 pinstrapping. The L6718 features a second power

manager bus to easily implement power management features as well as overspeeding

while the application is running. The power manager SMBus is operative after VREADY is

driven high at the end of the soft-start.

Once the controller is predisposed to use the SMBus interface, CONFIG2/SCL and

CONFIG3/SDA pins are set as digital input clock (SCL) and data (SDA).

SMBus interface communication is based on a two-wire clock and data which connect a

master to one or more slaves addressed separately. The master starts the SMBus

transaction and drives the clock and the data signals. The slave (L6718) receives the

transaction and acts accordingly. In the case of a reading command, the slave drives the

data signal to reply to the bus with a byte or a word.

The L6718 SMBus address for multi-phase and single-phase rails can be selected at startup

by the choice of the configuration mode and pinstrapping (see Table 14).

In CPU mode the SMBus address depends on the choice of SVID address which is 00h

typically but can be selected to 01h only in MRO (see Section 6.3.1).

In DDR mode the SMBus address depends on the status of Add_Dom selectable from

CONFIG1 pinstrapping (seeSection 6.6.4).

The single-phase rail in DDR mode can be addressed only in Jmode.

The L6718 SMBus commands are able to change dynamically the status of the voltage

regulator, the DPM strategy, the VFDE, and some protection thresholds, as shown in

Table 15.

Power SMBus protocol is based on the system management bus (SMBus) specification ver.

2.0 which can run up to 400 kHz.

Cycling VCC resets the register to the default configuration.

L6718 Datasheet(PDF) 42 Page - STMicroelectronics

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