ST7FOXA0 datasheet(30/123 Pages) STMICROELECTRONICS

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Supply, reset and clock management

ST7FOXA0

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6.2.2

Internal RC oscillator

In this mode, the tunable RC oscillator is used as main clock source. The two oscillator pins

have to be tied to ground.

The calibration is done through the RCCRH[7:0] and RCCRL[6:5] registers.

6.3

Reset sequence manager (RSM)

6.3.1

Introduction

The reset sequence manager includes three RESET sources as shown in Figure 12:

●

External RESET source pulse

●

Internal LVD RESET (Low Voltage Detection)

●

Internal WATCHDOG RESET

Note:

A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to Section 10.2.1 on page 84 for further details.

These sources act on the RESET pin and it is always kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory

mapping.

The basic RESET sequence consists of 3 phases as shown in Figure 11:

●

Active Phase depending on the RESET source

●

256 or 512 CPU clock cycle delay (see Table 6)

Caution:

When the ST7 is unprogrammed or fully erased, the Flash is blank and the Reset vector is

not programmed. For this reason, it is recommended to keep the RESET pin in low state

until programming mode is entered, in order to avoid unwanted behavior.

The 256 or 512 CPU clock cycle delay allows the oscillator to stabilize and ensures that

recovery has taken place from the Reset state. The shorter or longer clock cycle delay is

automatically selected depending on the clock source chosen by option byte.

The Reset vector fetch phase duration is 2 clock cycles.

Table 6.

CPU clock delay during Reset sequence

Clock source

CPU clock cycle delay

Internal RC 8 MHz Oscillator

512

Internal RC 32 kHz Oscillator

256

External clock connected to CLKIN pin

512

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