ST10F296E datasheet(98/346 Pages) STMICROELECTRONICS

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ST10F296E

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8.1

Programmable chip select timing control

The ST10F296E allows the user to adjust the position of the CSx line changes. By default

(after reset), the CSx lines change half a CPU clock cycle (7.8 ns at 64 MHz of CPU clock)

after the rising edge of ALE. With the CSCFG bit set in the SYSCON register the CSx lines

change with the rising edge of ALE, thus the CSx lines and the address lines change at the

same time (see Figure 18).

8.2

READY programmable polarity

The active level of the READY pin can be selected by software via the RDYPOL bit in the

BUSCONx registers.

When the READY function is enabled for a specific address window, each bus cycle within

this window must be terminated with the active level defined by the RDYPOL bit in the

associated BUSCON register.

BUSCONx registers are described in Section 23.10: System configuration registers on

page 280.

Note:

ST10F296E has no internal pull-up resistor on the READY pin.

Figure 18.

Chip select delay

Normal CSx

Address (P1)

ALE

Segment (P4)

Normal demultiplexed

Bus cycle

ALE lengthen demultiplexed

Bus cycle

Unlatched CSx

Read/write

Delay

Data

BUS (P0)

Read/write

Delay

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ST10F296E Datasheet(PDF) 98 Page - STMicroelectronics

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