ST10F296E datasheet(36/346 Pages) STMICROELECTRONICS

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Memory organization

ST10F296E

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4.7

CAN2

Address range 00’EE00h - 00’EEFFh is reserved for the CAN2 module access. CAN2 is

enabled by setting the XPEN bit (bit 2 of the SYSCON register) and the CAN2EN bit (bit 1 of

the new XPERCON register). Access to the CAN module use demultiplexed addresses and

a 16-bit data bus (only word access is possible). Two wait states give an access time of 62.5

ns at 64 MHz CPU clock. No tristate wait states are used.

Note:

If one or both CAN modules are used, Port 4 cannot be programmed to output all eight

segment address lines. Thus, only four segment address lines can be used, reducing the

external memory space to 5 Mbytes (1 Mbyte per CS line).

4.8

Real-time clock (RTC)

Address range 00’ED00h - 00’EDFFh is reserved for the RTC module access. The RTC is

enabled by setting the XPEN bit (bit 2 of the SYSCON register) and bit 4 of the XPERCON

(only word access is possible). Two waitstates give an access time of 62.5 ns at 64 MHz

CPU clock. No tristate waitstate is used.

4.9

Pulse-width modulation 1 (PWM1)

Address range 00’EC00h - 00’ECFFh is reserved for the PWM1 module access. The PWM1

is enabled by setting the XPEN bit (bit 2 of the SYSCON register) and bit 6 of the

XPERCON register. Access to the PWM1 module use demultiplexed addresses and a 16-bit

data bus (only word access is possible). Two waitstates give an access time of 62.5 ns at 64

MHz CPU clock. No tristate waitstate is used. Only word access is allowed.

4.10

ASC1

Address range 00’E900h - 00’E9FFh is reserved for the ASC1 module access. The ASC1 is

enabled by setting the XPEN bit (bit 2 of the SYSCON register) and bit 7 of the XPERCON

(only word access is possible). Two waitstates give an access time of 62.5 ns at 64 MHz

CPU clock. No tristate waitstate is used.

4.11

SSC1

Address range 00’E800h - 00’E8FFh is reserved for the SSC1 module access. The SSC1 is

enabled by setting the XPEN bit (bit 2 of the SYSCON register) and bit 8 of the XPERCON

(only word access is possible). Two waitstates give an access time of 62.5 ns at 64 MHz

CPU clock. No tristate waitstate is used.

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ST10F296E Datasheet(PDF) 36 Page - STMicroelectronics

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