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STM32F102xx Datasheet(PDF) 2 Page - STMicroelectronics |
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STM32F102xx Datasheet(HTML) 2 Page - STMicroelectronics |
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2 / 41 page  Contents STM32F10xx8 STM32F10xxB 2/41 DocID14574 Rev 13 Contents 1 ARM® 32-bit Cortex®-M3 limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Cortex-M3 limitations description for STM32F10xxx medium- density devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.1 Cortex-M3 LDRD with base in list may result in incorrect base register when interrupted or faulted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.2 Cortex-M3 event register is not set by interrupts and debug . . . . . . . . . . 8 1.1.3 Cortex-M3 BKPT in debug monitor mode can cause DFSR mismatch . . 8 1.1.4 Cortex-M3 may freeze for SLEEPONEXIT single instruction ISR . . . . . . 9 1.1.5 Interrupted loads to SP can cause erroneous behavior . . . . . . . . . . . . . . 9 1.1.6 SVC and BusFault/MemManage may occur out of order . . . . . . . . . . . 10 2 STM32F10xx8 and STM32F10xxB silicon limitations . . . . . . . . . . . . . 11 2.1 Voltage glitch on ADC input 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 Flash memory read after WFI/WFE instruction . . . . . . . . . . . . . . . . . . . . 13 2.3 Debug registers cannot be read by user software . . . . . . . . . . . . . . . . . . 13 2.4 Debugging Stop mode and system tick timer . . . . . . . . . . . . . . . . . . . . . . 14 2.5 Debugging Stop mode with WFE entry . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6 Wakeup sequence from Standby mode when using more than one wakeup source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.7 LSE start-up in harsh environments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.8 Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.8.1 USART1_RTS and CAN_TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.8.2 SPI1 in slave mode and USART2 in synchronous mode . . . . . . . . . . . . 16 2.8.3 SPI1 in master mode and USART2 in synchronous mode . . . . . . . . . . 16 2.8.4 SPI2 in slave mode and USART3 in synchronous mode . . . . . . . . . . . . 17 2.8.5 SPI2 in master mode and USART3 in synchronous mode . . . . . . . . . . 17 2.8.6 I2C2 with SPI2 and USART3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8.7 I2C1 with SPI1 remapped and used in master mode . . . . . . . . . . . . . . 18 2.8.8 I2C1 and TIM3_CH2 remapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.8.9 USARTx_TX pin usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.9 PVD and USB wakeup events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.10 Compatibility issue with latest compiler releases . . . . . . . . . . . . . . . . . . . 19 2.11 Boundary scan TAP: wrong pattern sent out after the “capture IR” state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 |
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