STM32F102xx datasheet(21/41 Pages) STMICROELECTRONICS

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STM32F10xx8 STM32F10xxB

STM32F10xx8 and STM32F10xxB silicon limitations

2.13

I2C peripheral

2.13.1

Some software events must be managed before the current byte is

being transferred

Description

When the EV7, EV7_1, EV6_1, EV6_3, EV2, EV8, and EV3 events are not managed before

the current byte is being transferred, problems may be encountered such as receiving an

extra byte, reading the same data twice or missing data.

Workarounds

When it is not possible to manage the EV7, EV7_1, EV6_1, EV6_3, EV2, EV8, and EV3

events before the current byte transfer and before the acknowledge pulse when changing

the ACK control bit, it is recommended to:

•

Workaround 1

Use the I2C with DMA in general, except when the Master is receiving a single byte.

•

Workaround 2

Use I2C interrupts and boost their priorities to the highest one in the application to

make them uninterruptible

•

Workaround 3 (only for EV6_1 and EV6_3 events used in method 2)

EV6_1 event (used in master receiver 2 bytes):

Stretch SCL line between ADDR bit is cleared and ACK is cleared:

ADDR=1

Configure SCL I/O as GPIO open-drain output low

Clear ADDR by reading SR1 register followed by reading SR3

Program ACK=0

Configure SCL I/O as Alternate Function open drain

EV6_3 event (used in master receiver 1 byte):

Stretch SCL line between ADDR bit is cleared and STOP bit programming:

ADDR=1

Program ACK=0

Configure SCL I/O as GPIO open-drain output low

Clear ADDR by reading SR1 register followed by reading SR3

Program STOP=1

Configure SCL I/O as Alternate Function open drain

STM32F102xx Datasheet(PDF) 21 Page - STMicroelectronics