STM32F102xx datasheet(39/41 Pages) STMICROELECTRONICS

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DocID14574 Rev 13

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STM32F10xx8 STM32F10xxB

Revision history

11-Jan-2010

Added limitations:

– Section 2.8.9: USARTx_TX pin usage

– Section 2.13.4: Wrong behavior of I2C peripheral in master mode

after a misplaced Stop

– Section 2.13.5: Mismatch on the “Setup time for a repeated Start

condition” timing parameter

– Section 2.13.6: Data valid time (tVD;DAT) violated without the OVR

flag being set

– Section 2.14.1: CRC still sensitive to communication clock when

SPI is in slave mode even with NSS high

– Section 2.19: USB packet buffer memory: over/underrun or

COUNTn_RX[9:0] field reporting incorrect number if APB1

frequency is below 13 MHz

Date code added to Figure 2 to Figure 6.

21-Jun-2010

Added Section 2.4: Debugging Stop mode and system tick timer

Added Section 2.5: Debugging Stop mode with WFE entry

Added Section 2.13.2: Wrong data read into data register

Updated Section 2.13.4: Wrong behavior of I2C peripheral in master

mode after a misplaced Stop

Added Section 2.15: USART peripheral

Updated Section 2.13.6: Data valid time (tVD;DAT) violated without

the OVR flag being set

22-Feb-2011

Updated workarounds in Section 2.13.1: Some software events must

be managed before the current byte is being transferred and

Section 2.13.2: Wrong data read into data register

Added section Section 2.15.6: nRTS signal abnormally driven low

after a protocol violation

17-Jun-2011

Added reference to revision code 1 in Table 1

Added Section 1.1.5: Interrupted loads to SP can cause erroneous

behavior

Section 1.1.6: SVC and BusFault/MemManage may occur out of

order

Added VFQFPN48 package to Figure 6

15-Nov-2011

Added reference to revision code 1 in Section 2.10: Compatibility

issue with latest compiler releases

Added Section 2.17: IWDG peripheral

Updated Section 2.15.6: nRTS signal abnormally driven low after a

protocol violation

Table 5. Document revision history (continued)

Date

Revision

Changes

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