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AD5308 Datasheet(PDF) 3 Page - Analog Devices

Part # AD5308
Description  2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
PDF  19 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5308 Datasheet(HTML) 3 Page - Analog Devices

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REV. B
AD5308/AD5318/AD5328
–3–
AC CHARACTERISTICS1
(VDD = 2.5 V to 5.5 V; RL = 2 k
to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless
otherwise noted.)
A, B Version
3
Parameter
2
Min
Typ
Max
Unit
Conditions/Comments
Output Voltage Settling Time
VREF = VDD = 5 V
AD5308
6
8
µs
1/4 Scale to 3/4 Scale Change (0x40 to 0xC0)
AD5318
7
9
µs
1/4 Scale to 3/4 Scale Change (0x100 to 0x300)
AD5328
8
10
µs
1/4 Scale to 3/4 Scale Change (0x400 to 0xC00)
Slew Rate
0.7
V/
µs
Major-Code Change Glitch Energy
12
nV-s
1 LSB Change around Major Carry
Digital Feedthrough
0.5
nV-s
Digital Crosstalk
0.5
nV-s
Analog Crosstalk
1
nV-s
DAC-to-DAC Crosstalk
3
nV-s
Multiplying Bandwidth
200
kHz
VREF = 2 V
± 0.1 V p-p. Unbuffered Mode.
Total Harmonic Distortion
–70
dB
VREF = 2.5 V
± 0.1 V p-p. Frequency = 10 kHz.
NOTES
1Guaranteed by design and characterization; not production tested.
2See the Terminology section.
3Temperature range (A, B Version): –40
°C to +105°C; typical at +25°C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2, 3
A, B Version
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
t1
33
ns min
SCLK Cycle Time
t2
13
ns min
SCLK High Time
t3
13
ns min
SCLK Low Time
t4
13
ns min
SYNC to SCLK Falling Edge Setup Time
t5
5
ns min
Data Setup Time
t6
4.5
ns min
Data Hold Time
t7
0
ns min
SCLK Falling Edge to
SYNC Rising Edge
t8
50
ns min
Minimum
SYNC High Time
t9
20
ns min
LDAC Pulsewidth
t10
20
ns min
SCLK Falling Edge to
LDAC Rising Edge
t11
0
ns min
SCLK Falling Edge to
LDAC Falling Edge
NOTES
1Guaranteed by design and characterization; not production tested.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of (V IL + VIH)/2.
3See Figures 2 and 3.
Specifications subject to change without notice.
SCLK
SYNC
DIN
DB15
DB0
LDAC1
LDAC2
NOTES
1 ASYNCHRONOUS LDAC UPDATE MODE
2 SYNCHRONOUS LDAC UPDATE MODE
t1
t2
t8
t3
t4
t5
t6
t9
t11
t7
t10
Figure 1. Serial Interface Timing Diagram



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