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873991 Datasheet(PDF) 11 Page - Integrated Device Technology |
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873991 Datasheet(HTML) 11 Page - Integrated Device Technology |
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11 / 18 page ![]() 873991 www.idt.com REV. A 8/25/15 11 873991 LOW VOLTAGE, LVCMOS/ LVPECL-TO-LVPECL/ECL CLOCK GENERATOR LVPECL CLOCK INPUT INTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5D show interface examples for the PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. FIGURE 5A. PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER FIGURE 5B. PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER FIGURE 5C. PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 5D. PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER HiPerClockS PCLK nPCLK PCLK/nPCLK 3.3V R2 50 R1 50 3.3V Zo = 50 Ohm CML 3.3V Zo = 50 Ohm PCLK/nPCLK 2.5V Zo = 60 Ohm SSTL HiPerClockS PCLK nPCLK R2 120 3.3V R3 120 Zo = 60 Ohm R1 120 R4 120 2.5V C2 R2 1K R5 100 Zo = 50 Ohm 3.3V 3.3V C1 R3 1K LVDS R4 1K HiPerClockS PCLK nPCLK R1 1K Zo = 50 Ohm 3.3V PCLK/nPCLK 3.3V HiPerClockS PCLK nPCLK R2 84 R3 125 Input Zo = 50 Ohm R4 125 R1 84 LVPECL 3.3V 3.3V Zo = 50 Ohm |
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