HPC16003 datasheet(12/36 Pages) NSC

12 / 36 page

Pin Descriptions (Continued)

B14

TS3

Timer Synchronous Output

B15

RDRDY

Read Ready Output for UPI Mode

When accessing external memory four bits of port B

are used as follows

B10

ALE

Address Latch Enable Output

B11

Write Output

B12

HBE

High Byte Enable OutputInput

(sampled at reset)

B15

Read Output

Port I is an 8-bit input port that can be read as general

purpose inputs and is also used for the following functions

NMI

Nonmaskable Interrupt Input

INT2

Maskable InterruptInput CaptureURD

INT3

Maskable InterruptInput CaptureUWR

INT4

Maskable InterruptInput Capture

MICROWIREPLUS Data Input

RDX

UART Data Input

Port D is an 8-bit input port that can be used as general

purpose digital inputs

Port P is a 4-bit output port that can be used as general

purpose data or selected to be controlled by timers 4

through 7 in order to generate frequency duty cycle and

pulse width modulated outputs

POWER SUPPLY PINS

VCC1 and

VCC2

Positive Power Supply

GND

Ground for On-Chip Logic

DGND

Ground for Output Buffers

Note

There are two electrically connected VCC pins on the chip GND and

DGND are electrically isolated Both VCC pins and both ground pins

must be used

CLOCK PINS

CKI

The Chip System Clock Input

CKO

The Chip System Clock Output (inversion of CKI)

Pins CKI and CKO are usually connected across an external

crystal

CK2

Clock Output (CKI divided by 2)

OTHER PINS

This is an active low open drain output that sig-

nals an illegal situation has been detected by the

Watch Dog logic

ST1

Bus Cycle Status Output indicates first opcode

fetch

ST2

Bus Cycle Status Output

indicates machine

states (skip interrupt and first instruction cycle)

RESET

is an active low input that forces the chip to re-

start and sets the ports in a TRI-STATE mode

RDYHLD has two uses selected by a software bit It’s ei-

ther a READY input to extend the bus cycle for

slower memories or a HOLD request input to put

the bus in a high impedance state for DMA pur-

poses

(no connection) do not connect anything to this

EXM

External memory enable (active high) disables

internal ROM and maps it to external memory

External

interrupt

with

vector

address

FFF1FFF0 (Risingfalling edge or highlow lev-

el sensitive) Alternately can be configured as

4th input capture

EXUI

External interrupt which is internally OR’ed with

the

UART

interrupt

with

vector

address

FFF3FFF2 (Active Low)

Connection Diagrams

Plastic and Ceramic Leaded Chip Carriers

TLDD8801 – 11

Top View

See NS Package Number EL68A or V68A

See Part Selection for Ordering Information

HPC16003 Datasheet(PDF) 12 Page - National Semiconductor (TI)

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