HPC16003 datasheet(19/36 Pages) NSC

19 / 36 page

Interrupt Arbitration

The HPC16083 contains arbitration logic to determine which

interrupt will be serviced first if two or more interrupts occur

simultaneously The arbitration ranking is given in Table III

The interrupt on RESET has the highest rank and is serv-

iced first

Interrupt Processing

Interrupts are serviced after the current instruction is com-

pleted except for the RESET which is serviced immediately

RESET and EXUI are level-LOW-sensitive interrupts and EI

is programmable for edge-(RISING or FALLING) or level-

(HIGH or LOW) sensitivity All other interrupts are edge-sen-

sitive NMI is positive-edge sensitive The external interrupts

on I2 I3 and I4 can be software selected to be rising or

falling edge External interrupt (EXUI) is shared with the

UART interrupt This interrupt is level-low sensitive To se-

lect this interrupt disable the ERI and ETI UART interrupt

bits in the ENUI register To select the UART interrupt leave

this pin floating or tie it high

Interrupt Control Registers

The HPC16083 allows the various interrupt sources and

conditions to be programmed This is done through the vari-

ous control registers A brief description of the different con-

trol registers is given below

INTERRUPT ENABLE REGISTER (ENIR)

RESET and the External Interrupt on I1 are non-maskable

interrupts The other interrupts can be individually enabled

or disabled Additionally a Global Interrupt Enable Bit in the

ENIR Register allows the Maskable interrupts to be collec-

tively enabled or disabled Thus in order for a particular

interrupt to request service both the individual enable bit

and the Global Interrupt bit (GIE) have to be set

INTERRUPT PENDING REGISTER (IRPD)

The IRPD register contains a bit allocated for each interrupt

vector The occurrence of specified interrupt trigger condi-

tions causes the appropriate bit to be set There is no indi-

cation of the order in which the interrupts have been re-

ceived The bits are set independently of the fact that the

interrupts may be disabled IRPD is a ReadWrite register

The bits corresponding to the maskable external interrupts

are normally cleared by the HPC16083 after servicing the

interrupts

For the interrupts from the on-board peripherals the user

has the responsibility of resetting the interrupt pending flags

through software

The NMI bit is read only and I2 I3 and I4 are designed as to

only allow a zero to be written to the pending bit (writing a

one has no affect) A LOAD IMMEDIATE instruction is to be

the only instruction used to clear a bit or bits in the IRPD

the other pending bits are not affected

INTERRUPT CONDITION REGISTER (IRCD)

Three bits of the register select the input polarity of the

external interrupt on I2 I3 and I4

Servicing the Interrupts

The Interrupt once acknowledged pushes the program

counter (PC) onto the stack thus incrementing the stack

pointer (SP) twice The Global Interrupt Enable bit (GIE) is

copied into the CGIE bit of the PSW register it is then reset

thus disabling further interrupts The program counter is

loaded with the contents of the memory at the vector ad-

dress and the processor resumes operation at this point At

the end of the interrupt service routine the user does a

RETI instruction to pop the stack and re-enable interrupts if

the CGIE bit is set or RET to just pop the stack if the CGIE

bit is clear and then returns to the main program The GIE

bit can be set in the interrupt service routine to nest inter-

rupts if desired

Figure 18 shows the Interrupt Enable Logic

RESET

The RESET input initializes the processor and sets ports A

and B in the TRI-STATE condition and port P in the LOW

state RESET is an active-low Schmitt trigger input The

processor vectors to FFFFFFFE and resumes operation at

the address contained at that memory location (which must

correspond to an on board location) The Reset vector ad-

dress must be between E000 and FFFF when using the

HPC16003

HPC16003 Datasheet(PDF) 19 Page - National Semiconductor (TI)

HPC16003 Datasheet(HTML) 19 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL