HPC16003 datasheet(18/36 Pages) NSC

18 / 36 page

HPC16003 Operating Modes (Continued)

TLDD8801 – 19

FIGURE 17 16-Bit External Memory

Wait States

The internal ROM can be accessed at the maximum operat-

ing frequency with one wait state With 0 wait states internal

ROM accesses are limited to

fC max

The HPC16083 provides four software selectable Wait

States that allow access to slower memories The Wait

States are selected by the state of two bits in the PSW

the instruction cycle allowing the user to interface with slow

memories and peripherals

Power Save Modes

Two power saving modes are available on the HPC16083

HALT and IDLE In the HALT mode all processor activities

are stopped In the IDLE mode the on-board oscillator and

timer T0 are active but all other processor activities are

stopped In either mode all on-board RAM registers and

IO are unaffected

HALT MODE

The HPC16083 is placed in the HALT mode under software

control by setting bits in the PSW All processor activities

including the clock and timers are stopped In the HALT

mode power requirements for the HPC16083 are minimal

and the applied voltage (VCC) may be decreased without

altering the state of the machine There are two ways of

exiting the HALT mode via the RESET or the NMI The

RESET input reinitializes the processor Use of the NMI in-

put will generate a vectored interrupt and resume operation

from that point with no initialization The HALT mode can be

enabled or disabled by means of a control register HALT

enable To prevent accidental use of the HALT mode the

HALT enable register can be modified only once

IDLE MODE

The HPC16083 is placed in the IDLE mode through the

PSW In this mode all processor activity except the on-

board oscillator and Timer T0 is stopped As with the HALT

mode the processor is returned to full operation by the

RESET or NMI inputs but without waiting for oscillator stabi-

lization A timer T0 overflow will also cause the HPC16083

to resume normal operation

HPC16083 Interrupts

Complex interrupt handling is easily accomplished by the

HPC16083’s vectored interrupt scheme There are eight

possible interrupt sources as shown in Table III

TABLE III Interrupts

Vector

Interrupt

Arbitration

Address

Source

Ranking

FFFFFFFE

RESET

FFFDFFFC

Nonmaskable external on

rising edge of I1 pin

FFFBFFFA

External interrupt on I2 pin

FFF9FFF8

External interrupt on I3 pin

FFF7FFF6

External interrupt on I4 pin

FFF5FFF4

Overflow on internal timers

FFF3FFF2

Internal on the UART

transmitreceive complete

or external on EXUI

FFF1FFF0

External interrupt on EI pin

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