16

AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial Temperature Range

NOTES:

1. ZZ input is LOW,

ADV is HIGH and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. For read cycles,

ADSP and ADSC function identically and are therefore interchangable.

Non-Burst Read Cycle Timing Waveform

CLK

ADSP

GW

, BWE, BWx

CE

ADDRESS

ADSC

OE

Av

Aw

Ax

Ay

Az

(Av)

(Aw)

(Ax)

(Ay)

5280 drw 10

,

Non-Burst Write Cycle Timing Waveform

CLK

ADSP

GW

CE

ADDRESS

ADSC

Av

Aw

Ax

Az

Ay

(Av)

(Aw)

(Ax)

(Az)

(Ay)

5280 drw 11

,

NOTES:

1. ZZ input is LOW,

ADV and OE are HIGH, and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. Although only

GW writes are shown, the functionality of BWE and BWx together is the same as GW.

4. For write cycles,

ADSP and ADSC have different limitations.