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L9660 Datasheet(PDF) 29 Page - STMicroelectronics

Part # L9660
Description  Quad squib driver ASIC for safety application
PDF  49 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L9660 Datasheet(HTML) 29 Page - STMicroelectronics

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L9660
Functional description
48
High side safing diagnostics
When the command is received the L9660 activates IHSS on the selected VRESx. The
diagnostics measures the difference between VSDIAG and VRESx. The internal
comparator detects open, short or normal condition based on the differential voltage
between VSDIAG and VRESx.
The results are reported in the next SPI message using bits HSS1 and HSS0 as indicated in
the following table. Once the command is issued the voltages are captured on the next
falling edge of CS_D.
Voltage measurement diagnostics (VRESx)
When the command is received the L9660 activates a comparator for the selected channel.
A 2 bit indication of the state of the VRESx pins is reported as indicated below. The results
are reported in the next SPI message. Once the command is issued the voltages are
captured on the next falling edge of CS_D.
Loss of power ground
When any of the power grounds (GND0 – 3) are lost, no deployment can occur on the
respective deployment channels because the low side driver is inactive. The high side driver
for the respective channel can still be activated.
A loss of ground condition on one or several channels does not affect the operation of the
remaining channels. When a loss of ground condition occurs, the source of the low side
MOS is floating. In this case, no current flows through the low side driver.
This condition is detected as a fault by a low side MOS diagnostic. No additional faults are
reported from any other diagnostic due to this condition.
Table 12. Diagnostic Mode HSS selection
Condition
HSS1
HSS0
(VSDIAG-VRESx) < VHSSSHORT_th
0
0
VHSSSHORT_th < (VSDIAG-VRESx) < VHSSOPEN_th
0
1
VHSSOPEN_th < (VSDIAG-VRESx)
1
1
Table 13. Diagnostic mode 3 VRESx selection
Condition
VR1
VR0
VRESx < VVRESXLO_th
0
0
VVRESXLO_th < VRESx < VVRESXHI_th
0
1
VVRESXHI_th < VRESx
1
1



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