AD9265-80EBZ datasheet(32/45 Pages) AD

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Data Sheet

AD9265

Rev. C | Page 31 of 44

Treat the clock input as an analog signal in cases in which

aperture jitter may affect the dynamic range of the AD9265. To

avoid modulating the clock signal with digital noise, separate

power supplies for clock drivers from the ADC output driver

supplies. Low jitter, crystal controlled oscillators make the best

clock sources. If the clock is generated from another type of source

(by gating, dividing, or another method), the output clock should

be retimed by the original clock at the last step.

Refer to Application Note AN-501, Aperture Uncertainty and

ADC System Performance, and Application Note AN-756,

Sampled Systems and the Effects of Clock Phase Noise and

Jitter, for more information about jitter performance as it

relates to ADCs.

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 81, the power dissipated by the AD9265 is

proportional to its sample rate. In CMOS output mode, the digital

power dissipation is determined primarily by the strength of the

digital drivers and the load on each output bit.

The maximum DRVDD current (IDRVDD) can be

approximately calculated as

IDRVDD = VDRVDD × CLOAD × fCLK × N

where N is the number of output bits (16 data bits plus 1 DCO,

in the case of the AD9265).

This maximum current occurs when every output bit switches on

every clock cycle, that is, a full-scale square wave at the Nyquist

frequency of fCLK/2. In practice, the DRVDD current is established

by the average number of output bits switching, which is

determined by the sample rate and the characteristics of the

analog input signal.

Reducing the capacitive load presented to the output drivers can

minimize digital power consumption. The data shown in Figure 81,

Figure 82, and Figure 83 were taken using a 70 MHz analog input

signal with a 5 pF load on each output driver.

0.5

TOTAL

POWER

IDRVDD

IAVDD

0.4

0.3

0.2

0.1

0.20

0.16

0.12

0.08

0.04

125

100

CLOCK FREQUENCY (MSPS)

Figure 81. AD9265-125 Power and Current vs. Sample Rate

0.5

0.4

0.3

0.2

0.1

0.20

0.16

0.12

0.08

0.04

105

CLOCK FREQUENCY (MSPS)

TOTAL

POWER

IDRVDD

IAVDD

Figure 82. AD9265-105 Power and Current vs. Sample Rate

0.5

0.4

0.3

0.2

0.1

0.15

0.12

0.09

0.06

0.03

ENCODE FREQUENCY (MSPS)

IAVDD

TOTAL

POWER

IDRVDD

Figure 83. AD9265-80 Power and Current vs. Sample Rate

By asserting PDWN (either through the SPI port or by asserting

the PDWN pin high), the AD9265 is placed in power-down mode.

In this state, the ADC typically dissipates 0.05 mW. During power-

down, the output drivers are placed in a high impedance state.

Asserting the PDWN pin low returns the AD9265 to its normal

operating mode.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering power-

down mode and then must be recharged when returning to normal

operation.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. In addition, when using the SPI

mode, the user can change the function of the external PDWN pin

to either place the part in power-down or standby mode. See the

Memory Map Register Description section for more details.

AD9265-80EBZ Datasheet(PDF) 32 Page - Analog Devices

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