AD9265-80EBZ datasheet(33/45 Pages) AD

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AD9265

Data Sheet

Rev. C | Page 32 of 44

DIGITAL OUTPUTS

The AD9265 output drivers can be configured to interface with

1.8 V CMOS logic families. The AD9265 can also be configured

for LVDS outputs using a DRVDD supply voltage of 1.8 V. The

AD9265 defaults to CMOS output mode but can be placed into

LVDS mode either by setting the LVDS pin high or by using the SPI

port to place the part into LVDS mode. Because most users do not

toggle between CMOS and LVDS mode during operation, use of

the LVDS pin is recommended to avoid any power-up loading

issues on the CMOS configured outputs.

In CMOS output mode, the output drivers are sized to provide

sufficient output current to drive a wide variety of logic families.

However, large drive currents tend to cause current glitches on

the supplies, which may affect converter performance. Applications

requiring the ADC to drive large capacitive loads or large

fanouts may require external buffers or latches.

In LVDS output mode two output drive levels can be selected,

either ANSI LVDS or reduced swing LVDS mode. Using the

reduced swing LVDS mode lowers the DRVDD current and

reduces power consumption. The reduced swing LVDS mode

can be selected by asserting the LVDS_RS pin or by selecting

this mode via the SPI port.

The output data format is selected for either offset binary or

twos complement by setting the SCLK/DFS pin when operating in

the external pin mode (see Table 12).

As detailed in Application Note AN-877, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary, twos complement, or gray code when using the SPI control.

Table 12. SCLK/DFS Mode Selection (External Pin Mode)

Voltage at

SCLK/DFS

SDIO/DCS

AGND

Offset binary (default)

DCS disabled

SVDD

Twos complement

DCS enabled (default)

Digital Output Enable Function (OEB)

The AD9265 has a flexible three-state ability for the digital output

pins. The three-state mode is enabled using the OEB pin or

through the SPI interface. If the OEB pin is low, the output data

drivers and DCOs are enabled. If the OEB pin is high, the output

data drivers and DCOs are placed in a high impedance state. This

OEB function is not intended for rapid access to the data bus.

Note that OEB is referenced to the output driver supply (DRVDD)

and should not exceed that supply voltage.

When using the SPI interface, the data and DCO outputs can be

three-stated by using the output enable bar bit in Register 0x14.

TIMING

The AD9265 provides latched data with a pipeline delay of

12 clock cycles (12.5 clock cycles in LVDS mode). Data outputs

are available one propagation delay (tPD) after the rising edge of

the clock signal.

Minimize the length of the output data lines and loads placed

on them to reduce transients within the AD9265. These

transients can degrade converter dynamic performance.

The lowest typical conversion rate of the AD9265 is 10 MSPS.

At clock rates below 10 MSPS, dynamic performance can degrade.

Data Clock Output (DCO)

The AD9265 provides a single data clock output (DCO) pin in

CMOS output mode and two differential data clock output (DCO)

pins in LVDS mode intended for capturing the data in an external

rising edge of DCO, unless the DCO clock polarity has been

changed via the SPI. In LVDS output mode, data is output as

double data rate with the odd numbered output bits transitioning

near the rising edge of DCO and the even numbered output bits

transitioning near the falling edge of DCO. See Figure 2 for a

graphical timing description.

Table 13. Output Data Format

Input (V)

Condition (V)

Offset Binary Output Mode

Twos Complement Mode

VIN+ − VIN−

< −VREF − 0.5 LSB

0000 0000 0000 0000

1000 0000 0000 0000

VIN+ − VIN−

= −VREF

0000 0000 0000 0000

1000 0000 0000 0000

VIN+ − VIN−

= 0

1000 0000 0000 0000

0000 0000 0000 0000

VIN+ − VIN−

= +VREF − 1.0 LSB

1111 1111 1111 1111

0111 1111 1111 1111

VIN+ − VIN−

> +VREF − 0.5 LSB

1111 1111 1111 1111

0111 1111 1111 1111

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