EPC635 datasheet(23/97 Pages) EPC

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5.3.2. Software reset via I2C

The epc635 can be software reset by sending I2C general call reset command (chapter 5.4.4.). Reset behaviour is similar to the RESET

pin. The chip is resetting including all analog and digital blocks at the same time.

5.3.3. Strap pins

The epc635 has output pins with dual/alternative functionality for PCB level flexible start-up configuration changing, called 'strap pins'. RE-

SET release is followed by a very short strap pin scanning step. The chip programs all of its strap pins as inputs with internal weak pull-

downs enabled for 4 osc_clk periods. If there is no external pull-up resistor connected, the corresponding strap pin will be scanned as logic

0 due to internal pull-down resistor. If there is an external pull-up resistor connected (Figure 14), it will override the internal pull-down and

corresponding pin will be scanned as logic 1. After the strap scan period, pins are programmed back as outputs so that they can be used

for their main function. Strap pins and their definitions are listed below (Table 11).

Strap pin

Definition

XSYNC_SAT_CFG

reserved

HSYNC_A1

Set A1 bit of 7-bit I2C slave device address (section 5.4.1.).

VSYNC_A0

Set A0 bit of 7-bit I2C slave device address (section 5.4.1.).

DCLK, DATA7 … DATA0

1, 13 … 10, 8, 7, 5, 4

reserved

Table 11: Strap pin definition

IMPORTANT:

For having the strap pin function correctly, there should be only one 10kΩ pull-up resistor per pin be active on the line during strap-scan

phase. No other pull-down/pull-up resistor, neither on the board nor in the pins of the application CPU shall be added or enabled, respect -

ively. Destination pins in the receiving device (application CPU) must be configured always as inputs during the start-up and never pro -

grammed as outputs at any time. If the receiving device by default enables its internal pull-down/up resistors during start-up phase, the ap -

plication SW must disable them before the reset is released and until the end of the strap-scan phase.

5.3.4. Start-up (Clock, PLL turn-on and EEPROM copy)

The epc635 starts using either the internal 4MHz oscillator OSC with a crystal/resonator (Figure 14) or an external 4MHz clock, followed by

an EEPROM copy sequence in parallel to the PLL turn-on phase. This is the factory default configuration.

Several configuration registers are modified by copying the EEPROM content (Figure 68 and Table 41, i.e. overwrite reset values). The

EEPROM copy step takes 340µs after the RESET is released. Note, the PLL lock time (stable < 32µs) is relatively faster compared to the

slower EEPROM copy.

Characteristics subject to change without notice

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Datasheet_epc635-V1.02

EPC635 Datasheet(PDF) 23 Page - Espros Photonics corp