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EPC635 Datasheet(PDF) 43 Page - Espros Photonics corp

Part # EPC635
Description  3D TOF Imager 160 x 60 Pixel
PDF  97 Pages
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Manufacturer  EPC [Espros Photonics corp]
Direct Link  http://www.espros.ch
Logo EPC - Espros Photonics corp

EPC635 Datasheet(HTML) 43 Page - Espros Photonics corp

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5.9.5. Detailed TCMI timing
DCLK
t
L
t
H
t
rfDCLK
t
rfDCLK
0.8 x VDDIO
0.2 x VDDIO
t
DCLK
VSYNC
HSYNC
Data out
Data out
Data out
Blanking
t
DDV
DATA [11:0]
XSYNC_SAT
t
DDC
t
Data valid
t
DV
Blanking
Figure 40: Detailed TCMI timing
Symbol
Parameter
Min.
Typ.
Max.
Units
tDCLK
TCMI readout clock: typ. fDCLK = 20MHz / max. fDCLK = 80MHz 1
50
12.5
ns
tDDV
Delay time after positive edge of DCLK until data are valid
2.0
ns
tDDC
Data start changing before positive edge of DCLK
1.7
ns
trfDCLK
Rise and fall time of DCLK, VSYNC, HSYNC, XSYNC, Data[11:0]
2.0
ns
tH
High period of DCLK 1
5.0
ns
tL
Low period of DCLK 1
3.5
ns
tData valid
Output data on the TCMI interface are valid (depends on DCLK)
8.8
ns
Table 24: TCMI timing parameters (CL = 20 pF max.)
Note 1: Is DCLK >40MHz, tH and tL value need to be reduced by 2.5ns for covering safely delay and jitter effects of this output.
R65
C4
1
2
3
4
5
6
7
8
t
PLL=12.5ns
R65
C5
R65
C6
R55
C7
VSYNC
HSYNC
DATA[11:0]
XSYNC_SAT
DCLK
pll_clk
TCMI detailed bus timing: DCLK=40MHz (pll_clk / 2)
R65
C4
1
2
3
4
5
6
7
8
t
PLL=12.5ns
R65
C5
R65
C6
VSYNC
HSYNC
DATA[11:0]
XSYNC_SAT
DCLK
pll_clk
TCMI detailed bus timing: DCLK=26.6MHz (pll_clk / 3)
R65
C4
1
2
3
4
5
6
7
8
t
PLL=12.5ns
R65
C5
VSYNC
HSYNC
DATA[11:0]
XSYNC_SAT
DCLK
pll_clk
TCMI detailed bus timing: DCLK=20MHz (default, pll_clk / 4)
R65
C4
1
2
3
4
5
6
7
8
t
PLL=12.5ns
R65
C6
VSYNC
HSYNC
DATA[11:0]
XSYNC_SAT
DCLK
pll_clk
TCMI detailed bus timing: DCLK=16MHz (pll_clk / 5)
Figure 41: TCMI timing examples with symmetric and asymmetric DCLK
© 2017 ESPROS Photonics Corporation
Characteristics subject to change without notice
43 / 97
Datasheet_epc635-V1.02
www.espros.com



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