13

power plane should support the input power and output power

nodes. Use copper filled polygons on the top and bottom

circuit layers for the phase nodes, but do not unnecessarily

oversize these particular islands. Since the phase nodes are

subjected to very high dV/dt voltages, the stray capacitor

formed between these islands and the surrounding circuitry

will tend to couple switching noise. Use the remaining printed

circuit layers for small signal wiring. The wiring traces from the

control IC to the MOSFET gate and source should be sized to

carry 2A peak currents.

Small Components Signal Layout Considerations

4. The VSNS1 and VSNS2 inputs should be bypassed with

a 1.0

µF capacitor close to their respective IC pins.

5. A ‘T’ filter consisting of a ‘split’ RSNS and a small, 100pF,

capacitor as shown in Figure 10, may be helpful in

reducing noise coupling into the ISEN input. For example,

if the calculated value of RSNS1 is 2.2k

Ω, dividing it as

shown with a 100pF capacitor provides filtering without

changing the current limit set point. For any calculated

value of RSNS, keep the value of the R9 portion to

approximately 200

Ω, and the remainder of the resistance

in the R19 position. The 200

Ω resistor and 100pF

capacitor provide effective filtering for noise above 8MHz.

This filter configuration may be helpful on both the 3.3V and

5V Main outputs.

6. The bypass capacitors for VBATT and the soft-start

their connecting pins on the control IC. Minimize any

leakage current paths from SDWN1 and SDWN2 nodes,

since the internal current source is only 5

µA.

7. Refer to the Application Note AN9915 for a recommended

component placement and interconnections.

Figure 11 shows an application circuit of a power supply for a

notebook PC microprocessor system. The power supply

provides +5V ALWAYS, +3.3V ALWAYS, +5.0V, +3.3V, and

on the circuit, including a Bill of Materials and circuit board

description, see Application Note AN9915. Also see Intersil’s

web site (www.intersil.com) for the latest information.

ISEN1

R19

R9

200

2K

C12

100pF

FROM PHASE

NODE

RSNS = R19 + R9

FIGURE 10. NOISE FILTER FOR ISEN1 INPUT

SDWNALL

GND

PGND1

LGATE1

UGATE1

ISEN1

PHASE1

Q3

Q5

+3.3V

VSEN2

UGATE2

PHASE2

Q2

C1

IPM6220

L2

+

+

+

C4

C3, 6, 10

R9, 19

+5V

100

µF

C22

330

µF

L1

HUF76112SK8

56

µF

3x1

µF

HUF76112SK8

2x330

µF

2.2K

8.2

µH

8.2

µH

GND

(5A)

4

5

10

2

6

1

21

23

22

20

19

17

13

14

C9

0.15

µF

BOOT1

PGND2

LGATE2

Q4

HUF76112SK8

7

8

ISEN2

R10, 11

2.2K

9

C7

0.15

µF

BOOT2

VBATT

+3.3V ALWAYS

3.3V ALWAYS

5V ALWAYS

11

SDWN2

C21, 32

D2

D1

24

3

HUF76112SK8

BAT54WT1

(5A)

(50mA)

+5V ALWAYS

(50mA)

C2

+

10

µF

0.022

µF

12

PGOOD

18

SDWN1

0.022

µF

C17

16

L4

2.7

µH

C16

Q5

+

15

VSEN3

GATE3

VSEN1

HUF76112SK8

C24, 33

2x47

µF

D3

R14

97.6K

24.9K

R13

BAT54WT1

+

L3

6.8

µH

22

µF

C36

FIGURE 11. APPLICATIONS CIRCUIT

+12V

(120mA)

IPM6220