IR3080

IR3080 THEORY OF OPERATION

Block Diagram

The Block diagram of the IR3080 is shown in Figure 6, and specific features are discussed in the following sections.

+

-

+

-

+

-

+

-

+

-

+

-

8.9V

+

-

+

-

+

-

+

-

BBFB

VOSNS-

IIN

OCSET

VID3

VID5

VCC

VIDFB

VRHOT

VID2

VID4

RMPOUT

VDRP

ROSC

VIDPWR

SS/DEL

VID1

VIDPGD

PWRGD

VBIAS

VID0

HOTSET

VDAC

LGND

FB

EAOUT

VCCVID

VIDDEL

IROSC

IROSC

VBIAS

IROSC

IROSC

IROSC

IROSC

IROSC

IROSC

IROSC

IROSC

IROSC

IROSC

IROSC

DISABLE

VRHOT

COMPARATOR

6uA

50%

DUTY

CYCLE

VCCVID

COMPARATOR

DISCHARGE

COMPARATOR

+

VID

CONTROL

VID = 11111X

ON

IDISCHG

VOLTAGE

PROPORTIONAL

TO ABSOLUTE

TEMPERATURE

OVER

CURRENT

CURRENT

SOURCE

GENERATOR

1.0V

VCCVID

REGULATOR

FAULT

LATCH

+

R

START

IOCSET

70uA

RAMP GENERATOR

6.85V

66uA

START

STOP

OVER-CURRENT

COMPARATOR

SS/DEL

DISCHARGE

IFB

4V

9.1V

-

IVTTDEL

SOFTSTART

CLAMP

5.0V

S

STOP

VBIAS

REGULATOR

VDRP

AMP

ICHG

ROSC

BUFFER

AMP

VCC

UVLO

COMPARATOR

0.2V

1.1V

-

VID DELAY

COMPARATOR

OFF

DELAY

COMPARATOR

90mV

1.3V

VID STEP-DOWN

VID DAC OUTPUT

ERROR

AMP

1.2V

Figure 6. IR3080 Block Diagram

VID Control

A 6-bit VID voltage compatible with VR 10, as shown in Table 1, is available at the VDAC pin. A detailed block

diagram of the VID control circuitry can be found in Figure 7. The VID pins are internally pulled up to VIDPWR pin

through 700Ω resistors. The VID input comparators, with 0.6V reference, monitor the VID pins and control the 6 bit

Digital-to-Analog Converter (DAC) whose output is sent to the VDAC buffer amplifier. The output of the buffer

amplifier is the VDAC pin. The VDAC voltage is post-package trimmed to compensate for the input offsets of the

Error Amplifier to provide a 0.5% system set-point accuracy. The actual VDAC voltage does not determine the

system accuracy and has a wider tolerance.

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