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sn1765 1765fas

Example: with VIN = 10V, VOUT = 5V and IOUT = 2A:

BOOST

= (

)()()

()()( )()

= ()(

)

()=

−

013 2

17 10

2 10 1 25 10

026 0 43

069

52 50

10 0 001

0 01

•.

•

Total power dissipation, PTOT, is 0.69 + 0.1 + 0.01 = 0.8W.

Thermal resistance for the LT1765 16-lead TSSOP ex-

posed pad package is influenced by the presence of

internal or backside planes. With a full plane under the

package, thermal resistance will be about 45

°C/W. With

no plane under the package, thermal resistance will in-

crease to about 110

°C/W. For the exposed pad package

θJC(PAD) = 10°C/W. Thermal resistance is dominated by

board performance. To calculate die temperature, use the

appropriate thermal resistance number and add in worst-

case ambient temperature:

TJ = TA + θJA (PTOT)

When estimating ambient, remember the nearby catch

diode will also be dissipating power.

DIODE

OUT

LOAD

= ()

−

()(

)

VF = Forward voltage of diode (assume 0.5V at 2A)

DIODE =

() −

()( )

05 10 5 2

Notice that the catch diode’s forward voltage contributes

a significant loss in the overall system efficiency. A larger,

lower VF diode can improve efficiency by several percent.

Typical thermal resistance of the board

θBis35°C/W.Atan

ambient temperature of 25

°C,

TJ = TA + θJA(PTOT) + θB(PDIODE)

TJ = 25 + 45 (0.8) + 35 (0.5) = 79°C

DIE TEMPERATURE MEASUREMENT

If a true die temperature is required, a measurement of the

SYNC to GND pin resistance can be used. The SYNC pin

resistance across temperature must first be calibrated,

with no significant output load, in an oven. An initial value

of 40k with a temperature coefficient of 0.16%/

°C is

typical. The same measurement can then be used in

operation to indicate the die temperature.

FREQUENCY COMPENSATION

Before starting on the theoretical analysis of frequency

response, the following should be remembered—the worse

the board layout, the more difficult the circuit will be to

stabilize. This is true of almost all high frequency analog

circuits, read the ‘LAYOUT CONSIDERATIONS’ section

first. Common layout errors that appear as stability prob-

lems are distant placement of input decoupling capacitor

and/or catch diode, and connecting the VC compensation

to a ground track carrying significant switch current. In

addition, the theoretical analysis considers only first order

ideal component behavior. For these reasons, it is impor-

tant that a final stability check is made with production

layout and components.

The LT1765 uses current mode control. This alleviates

many of the phase shift problems associated with the

inductor. The basic regulator loop is shown in Figure 7,

with both tantalum and ceramic capacitor equivalent cir-

cuits. The LT1765 can be considered as two gm blocks, the

error amplifier and the power stage.

APPLICATIO S I FOR ATIO

Figure 7. Model for Loop Response

1.2V

VSW

LT1765

GND

1765 F07

OUTPUT

ESR

500k

ERROR

AMPLIFIER

CURRENT MODE

POWER STAGE

gm = 5mho

gm =

850

µmho

ESL

CERAMIC

TANTALUM

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