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Figure 8 shows the overall loop response with a 330pF VC

capacitor and a typical 100

µF tantalum output capacitor.

The response is set by the following terms:

Error amplifier:

DC gain set by gm and RL = 850µ • 500k = 425.

Pole set by CF and RL = (2π • 500k • 330p)–1 = 965Hz.

Unity-gain set by CF and gm = (2π • 330p • 850µ–1)–1 =

410kHz.

Power stage:

DC gain set by gm and RL (assume 5Ω) = 5 • 5 = 25.

Pole set by COUT and RL = (2π • 100µ • 10)–1 = 159Hz.

Unity-gain set by COUT and gm = (2π • 100µ• 5–1)–1 = 8kHz.

Tantalum output capacitor:

Zero set by COUT and CESR = (2π • 100µ• 0.1)–1 = 15.9kHz.

The zero produced by the ESR of the tantalum output

capacitor is very useful in maintaining stability. Ceramic

output capacitors do not have a zero due to very low ESR,

but are dominated by their ESL. They form a notch in the

1MHz to 10MHz range. Without this zero, the VC pole must

be made dominant. A typical value of 2.2nF will achieve

this.

If better transient response is required, a zero can be

added to the loop using a resistor (RC) in series with the

compensation capacitor. As the value of RC is increased,

transient response will generally improve, but two effects

limit its value. First, the combination of output capacitor

ESR and a large RC may stop loop gain rolling off

altogether. Second, if the loop gain is not rolled suffi-

ciently at the switching frequency, output ripple will

perturb the VC pin enough to cause unstable duty cycle

switching similar to subharmonic oscillation. This may

not be apparent at the output. Small signal analysis will

not show this since a continuous time system is assumed.

If needed, an additional capacitor (CF) can be added to the

VC pin to form a pole at typically one fifth the switching

frequency (If RC = ~ 5k, CF = ~ 100pF)

When checking loop stability, the circuit should be oper-

ated over the application’s full voltage, current and tem-

perature range. Any transient loads should be applied and

the output voltage monitored for a well-damped behavior.

CONVERTER WITH BACKUP OUTPUT REGULATOR

In systems with a primary and backup supply, for ex-

ample, a battery powered device with a wall adapter input,

the output of the LT1765 can be held up by the backup

supply with its input disconnected. In this condition, the

SW pin will source current into the VIN pin. If the SHDN pin

is held at ground, only the shutdown current of 6

µA will be

pulled via the SW pin from the second supply. With the

SHDN pin floating, the LT1765 will consume its quiescent

operating current of 1mA. The VIN pin will also source

current to any other components connected to the input

line. If this load is greater than 10mA or the input could be

shorted to ground, a series Schottky diode must be added,

as shown in Figure 9. With these safeguards, the output

can be held at voltages up to the VIN absolute maximum

rating.

BUCK CONVERTER WITH ADJUSTABLE SOFT-START

Large capacitive loads or high input voltages can cause

high input currents at start-up. Figure 10 shows a circuit

that limits the dv/dt of the output at start-up, controlling

the capacitor charge rate. The buck converter is a typical

configuration with the addition of R3, R4, CSS and Q1. As

the output starts to rise, Q1 turns on, regulating switch

current via the VC pin to maintain a constant dv/dt at the

output. Output rise time is controlled by the current

through CSS defined by R4 and Q1’s VBE. Once the output

is in regulation, Q1 turns off and the circuit operates

normally. R3 is transient protection for the base of Q1.

APPLICATIO S I FOR ATIO

Figure 8. Overall Loop Response

FREQUENCY (Hz)

–20

–40

180

150

120

1765 F08

GAIN

PHASE

VOUT = 5V

COUT = 100µF, 0.1Ω

CC = 330pF

RC/CF = 0

ILOAD = 1A

10k

100

100k

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