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LTC1704/LTC1704B

1704bfa

APPLICATIO S I FOR ATIO

Gate Charge

Gate charge is amount of charge (essentially, the number

of electrons) that the LTC1704 needs to put into the gate

of an external MOSFET to turn it on. The easiest way to

visualize gate charge is to think of it as a capacitance from

the gate pin of the MOSFET to SW (for QT) or to PGND (for

QB). This capacitance is composed of MOSFET channel

charge, actual parasitic drain-source capacitance and

Miller-multiplied gate-drain capacitance, but can be ap-

proximated as a single capacitance from gate to source.

Regardless of where the charge is going, the fact remains

that it all has to come out of PVCC to turn the MOSFET gate

on, and when the MOSFET is turned back off, that charge

all ends up at ground. In the meanwhile, it travels through

the LTC1704’s gate drivers, heating them up. More power

lost!

In this case, the power is lost in little bite-sized chunks, one

chunk per switch per cycle, with the size of the chunk set

by the gate charge of the MOSFET. Every time the MOSFET

switches, another chunk is lost. Clearly, the faster the

clock runs, the more important gate charge becomes as a

loss term. Old fashioned switchers that ran at 20kHz could

pretty much ignore gate charge as a loss term. In the

550kHz LTC1704, gate charge loss can be a significant

efficiency penalty. Gate charge loss can be the dominant

loss term at medium load currents, especially with large

MOSFETs. Gate charge loss is also the primary cause of

power dissipation in the LTC1704 itself.

TG Charge Pump

There’s another nuance of MOSFET drive that the LTC1704

needs to get around. The LTC1704 is designed to use

N-channel MOSFETs for both QT and QB, primarily be-

cause N-channel MOSFETs generally cost less and have

lower RDS(ON) than similar P-channel MOSFETs. Turning

QB on is no big deal since the source of QB is attached to

PGND; the LTC1704 just switches the BG pin between

PGND and PVCC . Driving QT is another matter. The source

of QT is connected to SW which rises to VIN when QT is on.

To keep QT on, the LTC1704 must get TG one MOSFET

VGS(ON) above VIN. It does this by utilizing a floating driver

with the negative lead of the driver attached to SW (the

source of QT) and the PVCC lead of the driver coming out

separately at BOOST. An external 1

µF capacitor (CCP)

connected between SW and BOOST (Figure 2) supplies

power to BOOST when SW is high, and recharges itself

through DCP when SW is low. This simple charge pump

keeps the TG driver alive even as it swings well above VIN.

The value of the bootstrap capacitor CCP needs to be at

least 100 times that of the total input capacitance of the

topside MOSFET(s). For very large external MOSFETs (or

multiple MOSFETs in parallel), CCP may need to be in-

creased beyond the 1

µF value.

Input Supply

The BiCMOS process that allows the LTC1704 switcher

supply to include large MOSFET drivers on-chip also limits

the maximum input voltage to 6V. This limits the practical

maximum input supply to a loosely regulated 5V or 6V rail.

At the same time, the input supply needs to supply several

amps of current without excessive voltage drop. The input

supply must have regulation adequate to prevent sudden

load changes from causing the LTC1704 input voltage to

dip. In most typical applications where the LTC1704 is

generating a secondary low voltage logic supply, all of

these input conditions are met by the main system logic

supply when fortified with an input bypass capacitor.

Input Bypass Capacitor Selection

A typical LTC1704 circuit running from a 5V logic supply

might provide 1.6V at 10A at its switcher output. 5V to

1.6V implies a duty cycle of 32%, which means QT is on

32% of each switching cycle. During QT’s on-time, the

current drawn from the input equals the load current and

during the rest of the cycle, the current drawn from the

input is near zero. This 0A to 10A, 32% duty cycle pulse

train results in 4.66ARMS ripple current. At 550kHz, switch-

ing cycles last about 1.8

µs; most system logic supplies

have no hope of regulating output current with that kind of

speed. A local input bypass capacitor is required to make

up the difference and prevent the input supply from

dropping drastically when QT kicks on. This capacitor is

usually chosen for RMS ripple current capability and ESR

as well as value.

Consider our 10A example. The input bypass capacitor

gets exercised in three ways: its ESR must be low enough

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