MIC2186

Micrel

MIC2186

12

July 2002

The reverse voltage requirement of the diode is:

For the MIC2186, Schottky diodes are recommended when

they can be used. They have a lower forward voltage drop

than ultra-fast rectifier diodes, which lowers power dissipa-

tion and improves efficiency. They also do not have a recov-

ery time mechanism, which results in less ringing and noise

when the diode turns off. If the output voltage of the circuit

prevents the use of a Schottky diode, then only ultra-fast

recovery diodes should be used. Slower diodes will dissipate

more power in both the MOSFET and the diode. The will also

cause excessive ringing and noise when the diode turns off.

Reference, Enable and UVLO Circuits

The output drivers are enabled when the following conditions

are satisfied:

• The Vdd voltage (pin 10) is greater than its

undervoltage threshold.

• The voltage on the enable pin is greater than the

enable UVLO threshold.

The internal bias circuitry generates a 1.245V bandgap

reference for the voltage error amplifier and a 3V Vdd voltage

for the internal supply bus. The reference voltage in the

MIC2186 is buffered and brought out to pin 8. The Vref pin

must be bypassed to GND (pin 4) with a 0.1uf capacitor. The

Vdd pin must be decoupled to ground with a 1uf ceramic

capacitor.

The enable pin (pin 7) has two threshold levels, allowing the

MIC2186 to shut down in a micro-current mode, or turn off

output switching in standby mode. Below 0.9V, the device is

forced into a micro-power shutdown. If the enable pin is

between 0.9V and 1.5V the output gate drive is disabled but

the internal circuitry is powered on and the soft start pin

voltage is forced low. There is typically 135mV of hysteresis

below the 1.5V threshold to insure the part does not oscillate

on and off due to ripple voltage on the input. Raising the

enable voltage above the UVLO threshold of 1.5V enables

the output drivers and allows the soft start capacitor to

charge. The enable pin may be pulled up to VinA.

Oscillator & Sync

The internal oscillator is self-contained and requires no

external components. The HiDC and f/2 pins allow the user

to select from three different switching frequencies and two

maximum duty cycles. The chart in Table 1 shows the four

combinations that can be programmed along with the typical

minimum and maximum duty cycles.

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11

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3s

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2

Table 1

Minimum duty cycle becomes important in a boost converter

as the input voltage approaches the output voltage. At lower

duty cycles, the input voltage can be closer to the output

voltage without the output rising out of regulation.

A frequency foldback mode is enabled if the voltage on the

feedback pin (pin 6) is less than 0.3V. In frequency foldback

the oscillator frequency is reduced by approximately a factor

of 4. For the 400kHz setting, the oscillator runs at 100khz in

frequency foldback. For a 200kHz setting the oscillator runs

at approximately 50kHz and for a 100kHz setting, the oscil-

lator runs at approximately 25kHz.

The SYNC input (pin 11) allows the MIC2186 to synchronize

with an external CMOS or TTL clock signal. Depending on the

setting of the HiDC pin,the output frequency is either equal to

or 1/2 of the sync input frequency. If the HiDC level is low, the

output switching frequency is half the sync frequency. If the

HiDC level is high, the output switching frequency is equal to

the sync frequency.

The rising edge of the sync signal generates a reset signal in

the oscillator, which turns off the high-side gate drive output.

The low-side drive is turned on, restarting the switching cycle.

The sync signal is inhibited when the controller operates in

skip mode or frequency foldback. The sync signal frequency

must be greater than the maximum specified free running

frequency of the MIC2186. If the synchronizing frequency is

lower, double pulsing of the gate drive outputs will occur.

When not used, the sync pin must be connected to ground.

Table 2 shows the minimum recommended sync frequencies

for the different combinations of f/2 and HiDC inputs.

Figure 8a shows the timing between the external sync signal

(trace 2) and the low-side drive (trace 1) for a high level on the

HiDC pin. Figure 8b shows the timing between the external

sync signal (trace 2) and the low-side drive (trace 1) for a low

level on the HiDC pin. The sync frequency is twice the output

switching frequency.

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=

01

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=

C

N

Y

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11

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H

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0

0

2z

H

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0

5

2f

S

f

=

C

N

Y

S

00

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H

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0

0

2z

H

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8

4f

C

N

Y

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10

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H

k

0

0

1z

H

k

0

5

2f

C

N

Y

S

Table 2