PI6C106

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4

PS8546A

07/13/01

PD#TimingDiagram

The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is

an asynchronous active low input. This signal is synchronized internal by the PI6C106 prior to its control action of

powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD# is active

(low)allclocksaredriventoalowstateandheldpriortoturningofftheVCOsandtheCrystaloscillator.Thepoweronlatencyisguaranteed

tobelessthan3ms.ThepowerdownlatencyislessthanthreeCPUCLKcycles.PCI_STOP#andCPU_STOP#aredon’tcaresignalsduring

the power down operations.

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the PI6C106 device).

2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the PI6C106.

3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.

CPUCLK

(Internal)

CPUCLK

(0:2)

PCICLK_E, PCICLK_F,

PCICLK (0:4)

REF, IOAPIC

INTERNAL

VCOs

INTERNAL

CRYSTAL OSC.

PCICLK

(Internal)

PD#