ACE803ND

3-Pin Microprocessor Reset Circuits

VER 1.1

5

Detailed Description

A microprocessor’s (µP’s) reset input starts the µP in a known state. The ACE803ND asserts reset to

prevent code-execution errors during power-up, power-down, or brownout conditions. It asserts a reset

signal whenever the V

140ms after V

The ACE803ND uses an open-drain output.

Connect a pull-up resistor on the ACE803ND

’s RESET output to any supply between 0 and 6V.

Applications Information

In addition to issuing a reset to the µP during power-up, power-down, and brownout conditions, the

Figure 1 shows typical transient duration vs. reset comparator overdrive, for which the ACE803ND does

not generate a reset pulse. The graph was generated using a negative-going pulse applied to VCC,

starting 0.5V above the actual reset threshold and ending below it by the magnitude indicated (reset

have without causing a reset pulse. As the magnitude of the transient increases (goes farther below the

reset threshold), the maximum allowable pulse width decreases. Typically, for the ACE803NDL_,

ACE803NDM_ and ACE803NDJ_, a VCC transient that goes 100mV below the reset threshold and lasts

20µ s or less will not cause a reset pulse. A 0.1µF bypass capacitor mounted as close as possible to the

ACE803NDS/R/Z

ACE803NDL/M/J

Figure 1. Maximum Transient Duration without Causing a

Reset Pulse vs. Reset Comparator Overdrive