N/C

±IN

+IN

V±

V+

OUT

N/C

N/C

VS+

GND

VS±

GND

Ground (GND) plane on another layer

VOUT

VIN

GND

Run the input traces

as far away from

the supply lines

as possible

Use low-ESR, ceramic

bypass capacitor

RF

RG

Place components

close to device and to

each other to reduce

parasitic errors

+

VIN

VOUT

RG

RF

(Schematic Representation)

Use low-ESR,

ceramic bypass

capacitor

Copyright © 2016, Texas Instruments Incorporated

VOUT

25

OPA187, OPA2187, OPA4187

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SBOS807 – DECEMBER 2016

Product Folder Links: OPA187 OPA2187 OPA4187

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Copyright © 2016, Texas Instruments Incorporated

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

•

Low-ESR, 0.1-µF ceramic bypass capacitors must be connected between each supply pin and ground; place

the capacitors as close to the device as possible. A single bypass capacitor from V+ to ground is applicable

to single-supply applications.

•

To reduce parasitic coupling, run the input traces as far away from the supply lines as possible.

•

A ground plane helps distribute heat and reduces EMI noise pickup.

•

Place the external components as close to the device as possible. This configuration prevents parasitic errors

(such as the Seebeck effect) from occurring.

•

Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

10.2 Layout Example

Figure 48. Layout Example