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HT67F4892 Datasheet(PDF) 52 Page - Holtek Semiconductor Inc |
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HT67F4892 Datasheet(HTML) 52 Page - Holtek Semiconductor Inc |
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52 / 188 page  Rev. 1.00 5� �ove��e� ��� �01� Rev. 1.00 53 �ove��e� ��� �01� HT67F4892 Enhanced A/D Flash MCU with LCD & EEPROM HT67F4892 Enhanced A/D Flash MCU with LCD & EEPROM Bit2 LVRF:LVRFunctionResetFlag Describedelsewhere Bit1 LRF:LVRControlRegisterSoftwareResetFlag Describedelsewhere Bit0 WRF:WDTControlRegisterSoftwareResetFlag 0:Notoccur 1:Occurred ThisbitissethighbytheWDTControlregistersoftwareresetandclearedbythe applicationprogram.Notethatthisbitcanonlybeclearedtozerobytheapplication program. Watchdog Timer Operation TheWatchdogTimeroperatesbyprovidingadeviceresetwhenitstimeroverflows.Thismeans thatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallyclearthe WatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisis doneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumps toanunknownlocation,orentersanendlessloop,theseclearinstructionswillnotbeexecutedinthe correctmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.Therearefive bits,WE4~WE0,intheWDTCregistertooffertheenable/disablecontrolandresetcontrolofthe WatchdogTimer.TheWDTfunctionwillbedisabledwhentheWE4~WE0bitsaresettoavalueof 10101BwhiletheWDTfunctionwillbeenablediftheWE4~WE0bitsareequalto01010B.Ifthe WE4~WE0bitsaresettoanyothervalues,otherthan01010Band10101B,itwillresetthedevice afteradelaytime,tSRESET.Afterpoweronthesebitswillhaveavalueof01010B. WE4 ~ WE0 Bits WDT Function 10101B Disa�le 01010B Ena�le Any othe� values Reset MCU Watchdog Timer Enable/Disable Control Undernormalprogramoperation,aWatchdogTimertime-outwillinitialiseadeviceresetandset thestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimer time-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStack Pointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer. ThefirstisaWDTreset,whichmeansacertainvalueexcept01010Band10101Bwrittenintothe WE4~WE0bitfiled,thesecondisusingtheWatchdogTimersoftwareclearinstructionandthethird isviaaHALTinstruction. ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistouse thesingle"CLRWDT"instructiontocleartheWDT. Themaximumtimeoutperiodiswhenthe218divisionratioisselected.Asanexample,witha 32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround8 secondsforthe218divisionratio,andaminimumtimeoutof8msforthe28divisionration. “ CLR WDT”Inst�uction 8-stage Divide� WDT P�escale� WE�~WE0 �its WDTC Registe� Reset MCU LXT fSUB fSUB/�8 8-to-1 MUX CLR WS�~WS0 (fSUB/�8 ~ fSUB/�18) WDT Ti�e-out (�8/fSUB ~ �18/fSUB) LIRC M U X FSUBC FSUB�~FSUB0 �its “ HALT”Inst�uction Watchdog Timer |
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