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WM8912 Datasheet(PDF) 54 Page - Cirrus Logic |
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WM8912 Datasheet(HTML) 54 Page - Cirrus Logic |
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54 / 129 page  WM8912 Production Data w PD, Rev 4.1, February 2013 54 In master mode, LRCLK is derived from BCLK via a programmable division set by LRCLK_RATE. The BCLK input to this divider may be internal or external, allowing mixed master and slave modes. The direction of these signals and the clock frequencies are controlled as described in the “Digital Audio Interface Control” section. BCLK and LRCLK can be enabled as outputs in Slave mode, allowing mixed Master/Slave operation - see “Digital Audio Interface Control”. OPERATION WITH TDM Time division multiplexing (TDM) allows multiple devices to transfer data simultaneously on the same bus. The WM8912 supports TDM in master and slave modes for all data formats and word lengths. TDM is enabled and configured using register bits defined in the “Digital Audio Interface Control” section. Figure 27 TDM with WM8912 as Master Figure 28 TDM with other DAC as Master Figure 29 TDM with Processor as Master |
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