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WM8912 Datasheet(PDF) 88 Page - Cirrus Logic

Part # WM8912
Description  Ultra Low Power DAC with Headphone Driver
PDF  129 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8912 Datasheet(HTML) 88 Page - Cirrus Logic

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WM8912
Production Data
w
PD, Rev 4.1, February 2013
88
WSEQ
INDEX
REGISTER
ADDRESS
WIDTH
START
DATA
DELAY
EOS
DESCRIPTION
LINEOUTR_ENA_DLY = 1
(delay = 0.5625ms)
16 (10h)
R67 (43h)
4 bits
Bit 0
0Fh
Ch
0b
DCS_ENA_CHAN_0 = 1
DCS_ENA_CHAN_1 = 1
DCS_ENA_CHAN_2 = 1
DCS_ENA_CHAN_3 = 1
(delay = 0.5625ms)
17 (11h)
R68 (44h)
8 bits
Bit 0
F0h
0h
0b
DCS_TRIG_STARTUP_0 = 1
DCS_TRIG_STARTUP_1 = 1
DCS_TRIG_STARTUP_2 = 1
DCS_TRIG_STARTUP_3 = 1
(delay = 256.5ms)
18 (12h)
R255 (FFh)
1 bit
Bit 0
00h
0h
0b
Dummy Write for expansion
(delay = 0.5625ms)
19 (13h)
R90 (5Ah)
8 bits
Bit 0
77h
0h
0b
HPL_ENA_OUTP = 1
HPR_ENA_OUTP = 1
(delay = 0.5625ms)
20 (14h)
R94 (5Eh)
8 bits
Bit 0
77h
0h
0b
LINEOUTL_ENA_OUTP = 1
LINEOUTR_ENA_OUTP = 1
(delay = 0.5625ms)
21 (15h)
R90 (5Ah)
8 bits
Bit 0
FFh
0h
0b
HPL_RMV_SHORT = 1
HPR_RMV_SHORT = 1
(delay = 0.5625ms)
22 (16h)
R94 (5Eh)
8 bits
Bit 0
FFh
0h
1b
LINEOUTL_RMV_SHORT = 1
LINEOUTR_RMV_SHORT = 1
End of Sequence
23 (17h)
R255 (FFh)
1 bit
Bit 0
00h
0h
0b
Spare
24 (18h)
R255 (FFh)
1 bit
Bit 0
00h
0h
0b
Spare
Table 59 Start-up Sequence
SHUTDOWN SEQUENCE
The Shutdown sequence is initiated by writing 0119h to Register R111 (6Fh). This single operation
starts the Control Write Sequencer at Index Address 25 (19h) and executes the sequence defined in
Table 60.
For typical clocking configurations with MCLK=12.288MHz, this sequence takes approximately 350ms
to run.
WSEQ
INDEX
REGISTER
ADDRESS
WIDTH
START
DATA
DELAY
EOS
DESCRIPTION
25 (19h)
R94 (5Eh)
8 bits
Bit 0
77h
0h
0b
LINEOUTL_RMV_SHORT = 0
LINEOUTR_RMV_SHORT = 0
(delay = 0.5625ms)
26 (1Ah)
R90 (5Ah)
8 bits
Bit 0
77h
0h
0b
HPL_RMV_SHORT = 0
HPR_RMV_SHORT = 0
(delay = 0.5625ms)
27 (1Bh)
R90 (5Ah)
8 bits
Bit 0
00h
0h
0b
HPL_ENA_OUTP = 0
HPL_ENA_DLY = 0
HPL_ENA = 0
HPR_ENA_OUTP = 0
HPR_ENA_DLY = 0
HPR_ENA = 0



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