RT7302

13

DS7302-03 May 2015

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Copyright 2015 Richtek Technology Corporation. All rights reserved.

is a registered trademark of Richtek Technology Corporation.

Component

Range of Typical Value

(Tolerance < ±30%)

10

F to 33F

1

F to 4.7F

10pF to 10nF (Dimming)

1nF to 100nF (Non-dimming)

10pF to 22pF

NC to 22pF

10k

 to 22k

6.8M

 to 8.2M

47k

 to 56k

10k

 to 22k

10

 to 47

10

 to 100

Table 2. Suggested Component Values Range

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

the ambient temperature, and

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125

°C. The junction to

ambient thermal resistance,

SOP-8 package, the thermal resistance,

W on a standard JEDEC 51-3 two-layer thermal test board.

°C can be

calculated by the following formula :

°C − 25°C) / (206.9°C/W) = 0.48W for

SOP-8 package

The maximum power dissipation depends on the operating

resistance,

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

Figure 6. Derating Curve of Maximum Power Dissipation

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

025

50

75

100

125

Ambient Temperature (°C)

Two-Layer PCB

Layout Considerations

Aproper PCB layout can abate unknown noise interference

and EMI issue in the switching power supply. Please refer

to the guidelines when designing a PCB layout for

switching power supply.



The current path(1) from input capacitor, transformer,

frequency current loop. The path(2) from GD pin,

frequency current loop. They must be as short as

possible to decrease noise coupling and kept a space

to other low voltage traces, such as IC control circuit

paths, especially. Besides, the path(3) between

MOSFET ground(b) and IC ground(d) is recommended

to be as short as possible, too.



The path(4) from RCD snubber circuit to MOSFET is a

high switching loop. Keep it as small as possible.



The path(5) from input capacitor to HV pin is a high

voltage loop. Keep a space from path(5) to other low

voltage traces.



It is good for reducing noise, output ripple and EMI issue

to separate ground traces of input capacitor(a),

MOSFET(b), auxiliary winding(c) and IC control circuit(d).

Finally, connect them together on input capacitor

ground(a). The areas of these ground traces should be

kept large.