DM505LRBABF datasheet(157/290 Pages) TI1

157 / 290 page

A30 A31

B30 B31 C0 C1

C2 C3

C31

AHCLKX (Falling Edge Polarity)

AHCLKX (Rising Edge Polarity)

AFSR/X (Bit Width, 0 Bit Delay)

AFSR/X (Bit Width, 1 Bit Delay)

AFSR/X (Bit Width, 2 Bit Delay)

AFSR/X (Slot Width, 0 Bit Delay)

AFSR/X (Slot Width, 1 Bit Delay)

AFSR/X (Slot Width, 2 Bit Delay)

AXR[n] (Data In/Receive)

ACLKR/X (CLKRP = CLKXP = 0)(A)

ACLKR/X (CLKRP = CLKXP = 1)(B)

SPRS91v_McASP_01

157

DM505

www.ti.com

SPRS976D – NOVEMBER 2016 – REVISED JULY 2017

Submit Documentation Feedback

Specifications

For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP

receiver is configured for falling edge (to shift data in).

For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP

receiver is configured for rising edge (to shift data in).

Figure 5-43. McASP Input Timing

Table 5-55, Table 5-56, Table 5-57 and Figure 5-44 present Switching Characteristics Over

Recommended Operating Conditions for McASP1 to McASP3.

Table 5-55. Switching Characteristics Over Recommended Operating Conditions for McASP1 (1)

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(AHCLKX)

Cycle time, AHCLKX

tw(AHCLKX)

Pulse duration, AHCLKX high or low

0.5P -

2.5 (2)

tc(ACLKRX)

Cycle time, ACLKR/X

tw(ACLKRX)

Pulse duration, ACLKR/X high or low

0.5P -

2.5 (3)

td(ACLK-AFSXR)

Delay time, ACLKR/X transmit edge to AFSX/R output

valid

ACLKR/X int

ACLKR/X ext in

ACLKR/X ext out

22.2

DM505LRBABF Datasheet(PDF) 157 Page - Texas Instruments

DM505LRBABF Datasheet(HTML) 157 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL