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DM505LRBABF Datasheet(PDF) 101 Page - Texas Instruments |
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DM505LRBABF Datasheet(HTML) 101 Page - Texas Instruments |
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101 / 290 page  vddshv1, vddshv2, vddshv3, vddshv4, vddshv5, vddshv6 vdds18v Vdelta (Note1) SPRS916_ELCH_03 101 DM505 www.ti.com SPRS976D – NOVEMBER 2016 – REVISED JULY 2017 Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated Figure 5-3. vddshv* Supplies Falling After vdds18v Supplies Delta (1) Vdelta MAX = 2V 5.9.4 Clock Specifications NOTE For more information, see Power, Reset, and Clock Management / PRCM Subsystem Environment / External Clock Signals and Clock Management Functional Description section of the Device TRM. NOTE Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is still present in some clock or DPLL names. The device operation requires the following clocks: • The system clocks, SYS_CLK1(Mandatory) and SYS_CLK2(Optional) are the main clock sources of the device. They supply the reference clock to the DPLLs as well as functional clock to several modules. Figure 5-4 shows the external input clock sources and the output clocks to peripherals. |
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